Re: [PATCH] powerpc/40x: Add support for PPC40x boards with > 512MB SDRAM

[Benjamin Herrenschmidt <benh@kernel.crashing.org>]

On Wed, 2010-02-10 at 14:54 +0100, Stefan Roese wrote:
> This patch adds support for boards with more that 512MByte RAM. Currently
> only 512MB of memory are enabled in the DCCR/ICCR real-mode cache
> control registers. This patch now enables caching in real-mode for
> 2GByte.

Should we make that conditional to how much memory is populated ? Or it
doesn't matter ? I suppose we don't do IO accesses in real mode anyways
so no big deal...

Cheers,
Ben.

> Signed-off-by: Stefan Roese <sr@denx.de>
> Cc: Benjamin Herrenschmidt <benh@kernel.crashing.org>
> Cc: Josh Boyer <jwboyer@linux.vnet.ibm.com>
> ---
>  arch/powerpc/mm/40x_mmu.c |    4 ++--
>  1 files changed, 2 insertions(+), 2 deletions(-)
> 
> diff --git a/arch/powerpc/mm/40x_mmu.c b/arch/powerpc/mm/40x_mmu.c
> index 08dfa8e..65abfcf 100644
> --- a/arch/powerpc/mm/40x_mmu.c
> +++ b/arch/powerpc/mm/40x_mmu.c
> @@ -84,8 +84,8 @@ void __init MMU_init_hw(void)
>  	 * vectors and the kernel live in real-mode.
>  	 */
>  
> -        mtspr(SPRN_DCCR, 0xF0000000);	/* 512 MB of data space at 0x0. */
> -        mtspr(SPRN_ICCR, 0xF0000000);	/* 512 MB of instr. space at 0x0. */
> +        mtspr(SPRN_DCCR, 0xFFFF0000);	/* 2GByte of data space at 0x0. */
> +        mtspr(SPRN_ICCR, 0xFFFF0000);	/* 2GByte of instr. space at 0x0. */
>  }
>  
>  #define LARGE_PAGE_SIZE_16M	(1<<24)