From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from gate.crashing.org (gate.crashing.org [63.228.1.57]) (using TLSv1 with cipher DHE-RSA-AES256-SHA (256/256 bits)) (Client did not present a certificate) by ozlabs.org (Postfix) with ESMTPS id 18D3C1007E5 for ; Sat, 12 Jun 2010 20:45:54 +1000 (EST) Subject: Re: Request review of device tree documentation From: Benjamin Herrenschmidt To: Mitch Bradley In-Reply-To: <4C13430B.5000907@firmworks.com> References: <33BD8E86-9397-432A-97BF-F154812C157B@digitaldans.com> <4C13430B.5000907@firmworks.com> Content-Type: text/plain; charset="UTF-8" Date: Sat, 12 Jun 2010 20:45:29 +1000 Message-ID: <1276339529.1962.184.camel@pasglop> Mime-Version: 1.0 Cc: microblaze-uclinux@itee.uq.edu.au, devicetree-discuss , linuxppc-dev , Olof Johansson , Dan Malek , Jeremy Kerr List-Id: Linux on PowerPC Developers Mail List List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , On Fri, 2010-06-11 at 22:19 -1000, Mitch Bradley wrote: > It seems that many of the differences at the CPU level can be determined > by looking at "coprocessor" registers. For what purpose(s) do we need > to identify the core? That will inform our choice of a core ID schema. The primary thing I see would be architecture version compliance, though this is better carried additionally via a binary field in the header or a GPR at the entry point, to help the initial asm code to setup the MMU etc... before getting into C code. Cheers, Ben.