P1021MDS QE Ethernet Ports

P1021MDS QE Ethernet Ports

[Ioannis Kokkoris]

Hello=2C

we are seeing a strange behavior when trying to use the QE Ethernet interfa=
ces.
ENET5 (UCC5 - RMII) interface on P1021MDS boards does not come up if there =
is no physical link on the ENET1 (UCC1 - MII) Port.
It seems that interrupts from ENET5 are normally received but the link come=
s up and works properly only if we have physical connection on ENET1.=20

Can anyone think of a possible reason for this behavior=2C is there a way t=
o trace this problem?
I can provide any further information needed.

Any help would be appreciated=2C
Regards=2C
John

 		 	   		  =

RE: P1021MDS QE Ethernet Ports

[Ioannis Kokkoris]

> From: johnkokko@hotmail.com
> To: linuxppc-dev@lists.ozlabs.org
> Subject: P1021MDS QE Ethernet Ports
> Date: Wed=2C 1 Sep 2010 15:11:56 +0300
>
>
> Hello=2C
>
> we are seeing a strange behavior when trying to use the QE Ethernet inter=
faces.
> ENET5 (UCC5 - RMII) interface on P1021MDS boards does not come up if ther=
e is no physical link on the ENET1 (UCC1 - MII) Port.
> It seems that interrupts from ENET5 are normally received but the link co=
mes up and works properly only if we have physical connection on ENET1.
>
So far I found the following:

After adding traces=2C it seems that genphy_update_link() polls the correct=
 device=2C with the correct address (0x03)=2C but although a physical link =
is present in ENET5=2C the polling is not successful until there is a link =
in ENET1 (address 0x02)!

genphy_update_link: Dev: Micrel KS8041 ADD: 3 Status read 0x7849=A0 (withou=
t ENET1 Link)
genphy_update_link: Dev: Micrel KS8041 ADD: 3 Status read 0x786D=A0 (with=
=A0=A0=A0 ENET1 Link)

How does the MDIO of ENET1 affect the management of the physical interface =
in a different HW address?


> Can anyone think of a possible reason for this behavior=2C is there a way=
 to trace this problem?
> I can provide any further information needed.
>
> Any help would be appreciated=2C
> Regards=2C
> John
>
>
> _______________________________________________
> Linuxppc-dev mailing list
> Linuxppc-dev@lists.ozlabs.org
> https://lists.ozlabs.org/listinfo/linuxppc-dev
 		 	   		  =

RE: P1021MDS QE Ethernet Ports

[Haiying Wang]

On Thu, 2010-02-09 at 11:26 +0300, Ioannis Kokkoris wrote:
> > From: johnkokko@hotmail.com
> > To: linuxppc-dev@lists.ozlabs.org
> > Subject: P1021MDS QE Ethernet Ports
> > Date: Wed, 1 Sep 2010 15:11:56 +0300
> >
> >
> > Hello,
> >
> > we are seeing a strange behavior when trying to use the QE Ethernet interfaces.
> > ENET5 (UCC5 - RMII) interface on P1021MDS boards does not come up if there is no physical link on the ENET1 (UCC1 - MII) Port.
> > It seems that interrupts from ENET5 are normally received but the link comes up and works properly only if we have physical connection on ENET1.
> >
> So far I found the following:
> 
> After adding traces, it seems that genphy_update_link() polls the correct device, with the correct address (0x03), but although a physical link is present in ENET5, the polling is not successful until there is a link in ENET1 (address 0x02)!
> 
> genphy_update_link: Dev: Micrel KS8041 ADD: 3 Status read 0x7849  (without ENET1 Link)
> genphy_update_link: Dev: Micrel KS8041 ADD: 3 Status read 0x786D  (with    ENET1 Link)
> 
> How does the MDIO of ENET1 affect the management of the physical interface in a different HW address?
Which board version are you using? this problem is now fixed in the new board version but not available right now. You can connect two UECs for your current development.

> 
> > Can anyone think of a possible reason for this behavior, is there a way to trace this problem?
> > I can provide any further information needed.
> >
> > Any help would be appreciated,
> > Regards,
> > John
> >
> >
> > _______________________________________________
> > Linuxppc-dev mailing list
> > Linuxppc-dev@lists.ozlabs.org
> > https://lists.ozlabs.org/listinfo/linuxppc-dev
>  		 	   		  
> _______________________________________________
> Linuxppc-dev mailing list
> Linuxppc-dev@lists.ozlabs.org
> https://lists.ozlabs.org/listinfo/linuxppc-dev

RE: P1021MDS QE Ethernet Ports

[Ioannis Kokkoris]

> Subject: RE: P1021MDS QE Ethernet Ports
> From: Haiying.Wang@freescale.com
> To: johnkokko@hotmail.com
> CC: linuxppc-dev@lists.ozlabs.org
> Date: Thu=2C 2 Sep 2010 09:32:48 -0400
>
> On Thu=2C 2010-02-09 at 11:26 +0300=2C Ioannis Kokkoris wrote:
>>> From: johnkokko@hotmail.com
>>> To: linuxppc-dev@lists.ozlabs.org
>>> Subject: P1021MDS QE Ethernet Ports
>>> Date: Wed=2C 1 Sep 2010 15:11:56 +0300
>>>
>>>
>>> Hello=2C
>>>
>>> we are seeing a strange behavior when trying to use the QE Ethernet int=
erfaces.
>>> ENET5 (UCC5 - RMII) interface on P1021MDS boards does not come up if th=
ere is no physical link on the ENET1 (UCC1 - MII) Port.
>>> It seems that interrupts from ENET5 are normally received but the link =
comes up and works properly only if we have physical connection on ENET1.
>>>
>> So far I found the following:
>>
>> After adding traces=2C it seems that genphy_update_link() polls the corr=
ect device=2C with the correct address (0x03)=2C but although a physical li=
nk is present in ENET5=2C the polling is not successful until there is a li=
nk in ENET1 (address 0x02)!
>>
>> genphy_update_link: Dev: Micrel KS8041 ADD: 3 Status read 0x7849 (withou=
t ENET1 Link)
>> genphy_update_link: Dev: Micrel KS8041 ADD: 3 Status read 0x786D (with E=
NET1 Link)
>>
>> How does the MDIO of ENET1 affect the management of the physical interfa=
ce in a different HW address?
> Which board version are you using? this problem is now fixed in the new b=
oard version but not available right now.=20

We are using a board revision 2 (pilot version). Our main concern is whethe=
r this issue affects the working UCC1 eth interface performance.
Do you think that removing or pulling-down R79 (pin 21@U11) will fix the pr=
oblem with ENET1?

> You can connect two UECs for your current development.

Do you mean that changing the ENET1 interface from UCC1 to UCC3 in dts may =
solve the problem?

thank you for your reply=2C
John

 		 	   		  =

RE: P1021MDS QE Ethernet Ports

[Haiying Wang]

On Fri, 2010-03-09 at 10:05 +0300, Ioannis Kokkoris wrote:
> We are using a board revision 2 (pilot version). Our main concern is whether this issue affects the working UCC1 eth interface performance.
No, it won't affect the performance. We got line rate for performance
for UECs on this board.

> Do you think that removing or pulling-down R79 (pin 21@U11) will fix the problem with ENET1?
I don't know.

> > You can connect two UECs for your current development.
> 
> Do you mean that changing the ENET1 interface from UCC1 to UCC3 in dts may solve the problem?
No, I did not mean that. Only UCC1 and UCC5 are wired out for Ethernet
mode on this board, you can not change the UCC#. I meant, you should
have both UCC1/UCC5(ENET1/ENET5) connected with Ethernet cable.

Haiying