From: Dave Kleikamp <shaggy@linux.vnet.ibm.com>
To: Josh Boyer <jwboyer@linux.vnet.ibm.com>,
Benjamin Herrenschmidt <benh@kernel.crashing.org>
Cc: linuxppc-dev list <Linuxppc-dev@ozlabs.org>,
Dave Kleikamp <shaggy@linux.vnet.ibm.com>
Subject: [PATCH 0/2] powerpc/47x TLB optimization patches
Date: Fri, 24 Sep 2010 13:01:35 -0500 [thread overview]
Message-ID: <1285351297-9999-1-git-send-email-shaggy@linux.vnet.ibm.com> (raw)
These two patches reduce the frequency that the tlb caches are flushed in
hardware. Both the normal tlb cache and the "shadow" tlb cache, which
separates the tlbs for data and instruction access (dTLB and iTLB).
Dave Kleikamp (2):
476: Set CCR2[DSTI] to prevent isync from flushing shadow TLB
ppc: lazy flush_tlb_mm for nohash architectures
arch/powerpc/include/asm/reg_booke.h | 4 +
arch/powerpc/kernel/head_44x.S | 25 ++++++
arch/powerpc/mm/mmu_context_nohash.c | 154 ++++++++++++++++++++++++++++++---
arch/powerpc/mm/mmu_decl.h | 8 ++
arch/powerpc/mm/tlb_nohash.c | 28 +++++-
arch/powerpc/mm/tlb_nohash_low.S | 14 +++-
arch/powerpc/platforms/44x/Kconfig | 7 ++
arch/powerpc/platforms/44x/misc_44x.S | 26 ++++++
8 files changed, 249 insertions(+), 17 deletions(-)
--
1.7.2.2
next reply other threads:[~2010-09-24 18:01 UTC|newest]
Thread overview: 13+ messages / expand[flat|nested] mbox.gz Atom feed top
2010-09-24 18:01 Dave Kleikamp [this message]
2010-09-24 18:01 ` [PATCH 1/2] 476: Set CCR2[DSTI] to prevent isync from flushing shadow TLB Dave Kleikamp
2010-09-27 15:04 ` Josh Boyer
2010-09-27 15:26 ` Dave Kleikamp
2010-09-27 21:10 ` Benjamin Herrenschmidt
2010-09-27 21:15 ` Dave Kleikamp
2010-09-27 21:56 ` [PATCH 1/2] v2 " Dave Kleikamp
2010-10-12 19:40 ` Dave Kleikamp
2010-10-12 22:19 ` Josh Boyer
2010-09-24 18:01 ` [PATCH 2/2] ppc: lazy flush_tlb_mm for nohash architectures Dave Kleikamp
2010-10-14 0:52 ` Benjamin Herrenschmidt
2010-10-18 21:57 ` Dave Kleikamp
2010-10-18 23:34 ` Benjamin Herrenschmidt
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