From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from VA3EHSOBE008.bigfish.com (va3ehsobe006.messaging.microsoft.com [216.32.180.16]) (using TLSv1 with cipher AES128-SHA (128/128 bits)) (Client CN "mail.global.frontbridge.com", Issuer "Cybertrust SureServer Standard Validation CA" (verified OK)) by ozlabs.org (Postfix) with ESMTPS id D7D151007D2 for ; Fri, 5 Nov 2010 13:51:55 +1100 (EST) Received: from mail73-va3 (localhost.localdomain [127.0.0.1]) by mail73-va3-R.bigfish.com (Postfix) with ESMTP id AA8FFC88374 for ; Fri, 5 Nov 2010 02:51:51 +0000 (UTC) Received: from VA3EHSMHS022.bigfish.com (unknown [10.7.14.253]) by mail73-va3.bigfish.com (Postfix) with ESMTP id 41FC5A3804E for ; Fri, 5 Nov 2010 02:51:51 +0000 (UTC) Received: from de01smr01.freescale.net (de01smr01.freescale.net [10.208.0.31]) by az33egw01.freescale.net (8.14.3/8.14.3) with ESMTP id oA52pcqT006306 for ; Thu, 4 Nov 2010 19:51:38 -0700 (MST) Received: from zch01exm28.fsl.freescale.net (zch01exm28.ap.freescale.net [10.192.129.225]) by de01smr01.freescale.net (8.13.1/8.13.0) with ESMTP id oA537WYL019440 for ; Thu, 4 Nov 2010 22:07:33 -0500 (CDT) From: Lan Chunhe To: Subject: [PATCH 1/3] edac: Use ccsr_pci structure instead of hardcoded define Date: Fri, 5 Nov 2010 10:54:51 +0800 Message-ID: <1288925691-1217-1-git-send-email-b25806@freescale.com> MIME-Version: 1.0 Content-Type: text/plain Cc: Lan Chunhe , akpm@linux-foundation.org, "Kai.Jiang" , dougthompson@xmission.com List-Id: Linux on PowerPC Developers Mail List List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , There are some differences of register offset and definition between pci and pcie error management registers. While, some other pci/pcie error management registers are nearly the same. To merge pci and pcie edac code into one, it is easier to use ccsr_pci structure than the hardcoded define. So remove the hardcoded define and add pci/pcie error management register in ccsr_pci structure. Signed-off-by: Kai.Jiang Signed-off-by: Kumar Gala Signed-off-by: Lan Chunhe --- arch/powerpc/sysdev/fsl_pci.h | 54 +++++++++++++++++++++++++++++++--------- drivers/edac/mpc85xx_edac.h | 13 +-------- 2 files changed, 44 insertions(+), 23 deletions(-) diff --git a/arch/powerpc/sysdev/fsl_pci.h b/arch/powerpc/sysdev/fsl_pci.h index 8ad72a1..796985b 100644 --- a/arch/powerpc/sysdev/fsl_pci.h +++ b/arch/powerpc/sysdev/fsl_pci.h @@ -1,7 +1,7 @@ /* * MPC85xx/86xx PCI Express structure define * - * Copyright 2007 Freescale Semiconductor, Inc + * Copyright 2007, 2010 Freescale Semiconductor, Inc * * This program is free software; you can redistribute it and/or modify it * under the terms of the GNU General Public License as published by the @@ -14,6 +14,8 @@ #ifndef __POWERPC_FSL_PCI_H #define __POWERPC_FSL_PCI_H +#include + #define PCIE_LTSSM 0x0404 /* PCIE Link Training and Status */ #define PCIE_LTSSM_L0 0x16 /* L0 state */ #define PIWAR_EN 0x80000000 /* Enable */ @@ -71,18 +73,46 @@ struct ccsr_pci { */ struct pci_inbound_window_regs piw[3]; - __be32 pex_err_dr; /* 0x.e00 - PCI/PCIE error detect register */ - u8 res21[4]; - __be32 pex_err_en; /* 0x.e08 - PCI/PCIE error interrupt enable register */ - u8 res22[4]; - __be32 pex_err_disr; /* 0x.e10 - PCI/PCIE error disable register */ - u8 res23[12]; - __be32 pex_err_cap_stat; /* 0x.e20 - PCI/PCIE error capture status register */ +/* Merge PCI/PCI Express error management registers */ + __be32 pex_err_dr; /* 0x.e00 + * - PCI/PCIE error detect register + */ + __be32 pex_err_cap_dr; /* 0x.e04 + * - PCI error capture disabled register + * - PCIE has no this register + */ + __be32 pex_err_en; /* 0x.e08 + * - PCI/PCIE error interrupt enable register + */ + __be32 pex_err_attrib; /* 0x.e0c + * - PCI error attributes capture register + * - PCIE has no this register + */ + __be32 pex_err_disr; /* 0x.e10 + * - PCI error address capture register + * - PCIE error disable register + */ + __be32 pex_err_ext_addr; /* 0x.e14 + * - PCI error extended addr capture register + * - PCIE has no this register + */ + __be32 pex_err_dl; /* 0x.e18 + * - PCI error data low capture register + * - PCIE has no this register + */ + __be32 pex_err_dh; /* 0x.e1c + * - PCI error data high capture register + * - PCIE has no this register + */ + __be32 pex_err_cap_stat; /* 0x.e20 + * - PCI gasket timer register + * - PCIE error capture status register + */ u8 res24[4]; - __be32 pex_err_cap_r0; /* 0x.e28 - PCIE error capture register 0 */ - __be32 pex_err_cap_r1; /* 0x.e2c - PCIE error capture register 0 */ - __be32 pex_err_cap_r2; /* 0x.e30 - PCIE error capture register 0 */ - __be32 pex_err_cap_r3; /* 0x.e34 - PCIE error capture register 0 */ + __be32 pex_err_cap_r0; /* 0x.e28 - PCIE error capture register 0 */ + __be32 pex_err_cap_r1; /* 0x.e2c - PCIE error capture register 1 */ + __be32 pex_err_cap_r2; /* 0x.e30 - PCIE error capture register 2 */ + __be32 pex_err_cap_r3; /* 0x.e34 - PCIE error capture register 3 */ }; extern int fsl_add_bridge(struct device_node *dev, int is_primary); diff --git a/drivers/edac/mpc85xx_edac.h b/drivers/edac/mpc85xx_edac.h index cb24df8..099581d 100644 --- a/drivers/edac/mpc85xx_edac.h +++ b/drivers/edac/mpc85xx_edac.h @@ -1,5 +1,7 @@ /* * Freescale MPC85xx Memory Controller kenel module + * Copyright (c) 2010 Freescale Semiconductor, Inc. + * * Author: Dave Jiang * * 2006-2007 (c) MontaVista Software, Inc. This file is licensed under @@ -131,17 +133,6 @@ #define PCI_EDE_PERR_MASK (PCI_EDE_TGT_PERR | PCI_EDE_MST_PERR | \ PCI_EDE_ADDR_PERR) -#define MPC85XX_PCI_ERR_DR 0x0000 -#define MPC85XX_PCI_ERR_CAP_DR 0x0004 -#define MPC85XX_PCI_ERR_EN 0x0008 -#define MPC85XX_PCI_ERR_ATTRIB 0x000c -#define MPC85XX_PCI_ERR_ADDR 0x0010 -#define MPC85XX_PCI_ERR_EXT_ADDR 0x0014 -#define MPC85XX_PCI_ERR_DL 0x0018 -#define MPC85XX_PCI_ERR_DH 0x001c -#define MPC85XX_PCI_GAS_TIMR 0x0020 -#define MPC85XX_PCI_PCIX_TIMR 0x0024 - struct mpc85xx_mc_pdata { char *name; int edac_idx; -- 1.5.4.5