From: Benjamin Herrenschmidt <benh@kernel.crashing.org>
To: Scott Wood <scottwood@freescale.com>
Cc: linuxppc-dev@lists.ozlabs.org
Subject: Re: [PATCH 2/7] powerpc/mm: 64-bit 4k: use a PMD-based virtual page table
Date: Tue, 24 May 2011 12:52:44 +1000 [thread overview]
Message-ID: <1306205564.7481.210.camel@pasglop> (raw)
In-Reply-To: <20110523183100.36c54904@schlenkerla.am.freescale.net>
On Mon, 2011-05-23 at 18:31 -0500, Scott Wood wrote:
> On Tue, 24 May 2011 06:51:01 +1000
> Benjamin Herrenschmidt <benh@kernel.crashing.org> wrote:
>
> > Is your linear mapping bolted ? If it is you may be able to cut out most
> > of the save/restore stuff (SRR0,1, ...) since with a normal walk you
> > won't take nested misses.
>
> It is bolted -- we ignore anything we can't map with 16 entries. The only
> semi-realistic case I can think of where we might bump into that (and thus
> want non-bolted memory), especially with more than negligible loss compared
> to the size of memory, is AMP with a non-zero start address where we have
> to stick with smaller pages due to alignment. Even so, 16 times the
> alignment of the start of RAM doesn't seem that unreasonable a limit. The
> 32-bit limit of 3 entries for lowmem is a bit more troublesome there.
Ok so in this case, it might be worth doing a separate of TLB miss
handlers without all the context save/restore business... would also
make re-entrant CRITs and MCs easier to deal with.
Cheers,
Ben.
next prev parent reply other threads:[~2011-05-24 2:52 UTC|newest]
Thread overview: 27+ messages / expand[flat|nested] mbox.gz Atom feed top
2011-05-18 21:04 [PATCH 1/7] powerpc/mm: 64-bit 4k: use page-sized PMDs Scott Wood
2011-05-18 21:05 ` [PATCH 2/7] powerpc/mm: 64-bit 4k: use a PMD-based virtual page table Scott Wood
2011-05-18 21:33 ` Benjamin Herrenschmidt
2011-05-20 20:57 ` Scott Wood
2011-05-20 22:15 ` Benjamin Herrenschmidt
2011-05-23 18:54 ` Scott Wood
2011-05-23 20:51 ` Benjamin Herrenschmidt
2011-05-23 23:31 ` Scott Wood
2011-05-24 2:52 ` Benjamin Herrenschmidt [this message]
2011-05-18 21:05 ` [PATCH 3/7] powerpc/mm: 64-bit tlb miss: get PACA from memory rather than SPR Scott Wood
2011-05-18 21:05 ` [PATCH 4/7] powerpc/mm: 64-bit: Don't load PACA in normal TLB miss exceptions Scott Wood
2011-05-18 21:05 ` [PATCH 5/7] powerpc/mm: 64-bit: don't handle non-standard page sizes Scott Wood
2011-05-18 21:36 ` Benjamin Herrenschmidt
2011-05-18 21:50 ` Scott Wood
2011-05-18 21:54 ` Benjamin Herrenschmidt
2011-05-18 21:05 ` [PATCH 6/7] powerpc/mm: 64-bit: tlb handler micro-optimization Scott Wood
2011-05-18 21:37 ` Benjamin Herrenschmidt
2011-05-18 21:51 ` Scott Wood
2011-05-18 21:54 ` Benjamin Herrenschmidt
2011-05-18 22:27 ` Scott Wood
2011-05-18 21:05 ` [PATCH 7/7] powerpc/e5500: set MMU_FTR_USE_PAIRED_MAS Scott Wood
2011-05-18 21:38 ` Benjamin Herrenschmidt
2011-05-18 21:52 ` Scott Wood
2011-05-18 21:58 ` Benjamin Herrenschmidt
2011-05-18 21:32 ` [PATCH 1/7] powerpc/mm: 64-bit 4k: use page-sized PMDs Benjamin Herrenschmidt
2011-05-18 21:46 ` Scott Wood
2011-05-18 21:52 ` Benjamin Herrenschmidt
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