From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from gate.crashing.org (gate.crashing.org [63.228.1.57]) (using TLSv1 with cipher DHE-RSA-AES256-SHA (256/256 bits)) (Client did not present a certificate) by ozlabs.org (Postfix) with ESMTPS id EAC4DB6F9D for ; Wed, 25 May 2011 07:43:36 +1000 (EST) Subject: Re: Kernel cannot see PCI device From: Benjamin Herrenschmidt To: Prashant Bhole In-Reply-To: References: <1305846751.7481.55.camel@pasglop> Content-Type: text/plain; charset="UTF-8" Date: Wed, 25 May 2011 07:43:08 +1000 Message-ID: <1306273388.7481.240.camel@pasglop> Mime-Version: 1.0 Cc: Bjorn Helgaas , "linux-pci@vger.kernel.org" , Stefan Roese , linuxppc-dev , Tirumala Marri List-Id: Linux on PowerPC Developers Mail List List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , On Tue, 2011-05-24 at 10:25 +0530, Prashant Bhole wrote: > Fixed the problem by soft resetting the PCIe port in the function > ppc460ex_pciex_port_init_hw(). > Is it a right thing to do? > Following is the patch for kernel 2.6.38.4: > -------------------------------------------------------------------------------------- > --- linux-2.6.38.4/arch/powerpc/sysdev/ppc4xx_pci.c.orig 2011-05-24 > 10:02:38.000000000 +0530 > +++ linux-2.6.38.4/arch/powerpc/sysdev/ppc4xx_pci.c 2011-05-24 > 10:07:17.000000000 +0530 > @@ -876,6 +876,20 @@ > u32 val; > u32 utlset1; > > + switch (port->index) > + { > + case 0: > + mtdcri(SDR0, PESDR0_460EX_PHY_CTL_RST, 0x0); > + mdelay(10); > + break; > + case 1: > + mtdcri(SDR0, PESDR1_460EX_PHY_CTL_RST, 0x0); > + mdelay(10); > + break; > + default: > + break; > + } > + > if (port->endpoint) > val = PTYPE_LEGACY_ENDPOINT << 20; > else > -------------------------------------------------------------------------------------- Well, it's odd that you'd have to do that, maybe something the bootloader is doing ? I personally don't mind but I'd like Stefan and/or Tirumala opinion on this. Cheers, Ben.