[PATCH 3/4] powerpc/85xx: Merge PCI/PCI Express error management registers

[Shaohui Xie <Shaohui.Xie@freescale.com>]

From: Kai.Jiang <Kai.Jiang@freescale.com>

There are some differences of register offset and definition between
pci and pcie error management registers. While, some other pci/pcie
error management registers are nearly the same.

Signed-off-by: Kai.Jiang <Kai.Jiang@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
Signed-off-by: Shaohui Xie <Shaohui.Xie@freescale.com>
---
 arch/powerpc/sysdev/fsl_pci.h |   31 +++++++++++++++++++++++++------
 1 files changed, 25 insertions(+), 6 deletions(-)

difg --gite a/arch/powerpc/sysdev/fsl_pci.h b/arch/powerpc/sysdev/fsl_pci.h
index a39ed5c..60a76e9 100644
--- a/arch/powerpc/sysdev/fsl_pci.h
+++ b/arch/powerpc/sysdev/fsl_pci.h
@@ -74,13 +74,32 @@ struct ccsr_pci {
  */
 	struct pci_inbound_window_regs piw[4];
 
+/* Merge PCI/PCI Express error management registers */
 	__be32	pex_err_dr;		/* 0x.e00 - PCI/PCIE error detect register */
-	u8	res21[4];
-	__be32	pex_err_en;		/* 0x.e08 - PCI/PCIE error interrupt enable register */
-	u8	res22[4];
-	__be32	pex_err_disr;		/* 0x.e10 - PCI/PCIE error disable register */
-	u8	res23[12];
-	__be32	pex_err_cap_stat;	/* 0x.e20 - PCI/PCIE error capture status register */
+	__be32	pex_err_cap_dr;		/* 0x.e04 */
+					/* - PCI error capture disabled register */
+					/* - PCIE has no this register */
+	__be32	pex_err_en;		/* 0x.e08 */
+					/* - PCI/PCIE error interrupt enable register*/
+	__be32	pex_err_attrib;		/* 0x.e0c */
+					/* - PCI error attributes capture register */
+					/* - PCIE has no this register */
+	__be32	pex_err_disr;		/* 0x.e10 */
+					/* - PCI error address capture register */
+					/* - PCIE error disable register */
+	__be32	pex_err_ext_addr;	/* 0x.e14 */
+					/* - PCI error extended addr capture register*/
+					/* - PCIE has no this register */
+	__be32	pex_err_dl;		/* 0x.e18 */
+					/* - PCI error data low capture register */
+					/* - PCIE has no this register */
+	__be32	pex_err_dh;		/* 0x.e1c */
+					/* - PCI error data high capture register */
+					/* - PCIE has no this register */
+	__be32	pex_err_cap_stat;	/* 0x.e20 */
+					/* - PCI gasket timer register */
+					/* - PCIE error capture status register */
+
 	u8	res24[4];
 	__be32	pex_err_cap_r0;		/* 0x.e28 - PCIE error capture register 0 */
 	__be32	pex_err_cap_r1;		/* 0x.e2c - PCIE error capture register 0 */
-- 
1.6.4