From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from DB3EHSOBE001.bigfish.com (db3ehsobe005.messaging.microsoft.com [213.199.154.143]) (using TLSv1 with cipher AES128-SHA (128/128 bits)) (Client CN "mail.global.frontbridge.com", Issuer "Microsoft Secure Server Authority" (not verified)) by ozlabs.org (Postfix) with ESMTPS id 6C06EB725D for ; Tue, 7 Feb 2012 06:18:05 +1100 (EST) From: Timur Tabi To: , Subject: [PATCH] powerpc/fsl: add PAMUBYPENR register definition to fsl_guts.h Date: Mon, 6 Feb 2012 13:17:52 -0600 Message-ID: <1328555872-9616-1-git-send-email-timur@freescale.com> MIME-Version: 1.0 Content-Type: text/plain List-Id: Linux on PowerPC Developers Mail List List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Add a defintion of register PAMUBYPENR (offset 0x604) to the global utilities structure. PAMUBYPENR is the PAMU bypass enable register. It contains control bits for enabling bypass mode on each PAMU. Signed-off-by: Timur Tabi --- arch/powerpc/include/asm/fsl_guts.h | 4 +++- 1 files changed, 3 insertions(+), 1 deletions(-) diff --git a/arch/powerpc/include/asm/fsl_guts.h b/arch/powerpc/include/asm/fsl_guts.h index bebd124..a9a85ef 100644 --- a/arch/powerpc/include/asm/fsl_guts.h +++ b/arch/powerpc/include/asm/fsl_guts.h @@ -85,7 +85,9 @@ struct ccsr_guts_86xx { u8 res0c4[0x224 - 0xc4]; __be32 iodelay1; /* 0x.0224 - IO delay control register 1 */ __be32 iodelay2; /* 0x.0228 - IO delay control register 2 */ - u8 res22c[0x800 - 0x22c]; + u8 res22c[0x604 - 0x22c]; + __be32 pamubypenr; /* 0x.0604 - PAMU bypass enable register */ + u8 res608[0x800 - 0x608]; __be32 clkdvdr; /* 0x.0800 - Clock Divide Register */ u8 res804[0x900 - 0x804]; __be32 ircr; /* 0x.0900 - Infrared Control Register */ -- 1.7.3.4