[PATCH 1/4] powerpc/85xx: Add a head file for cpu type detection

[PATCH 1/4] powerpc/85xx: Add a head file for cpu type detection

[Zhao Chenhui]

From: chenhui zhao <chenhui.zhao@freescale.com>

The workarounds need to detect the cpu type. Add these macros
and inline routines to help cpu type detection in runtime.

Signed-off-by: Zhao Chenhui <chenhui.zhao@freescale.com>
Signed-off-by: Li Yang <leoli@freescale.com>
---
 arch/powerpc/include/asm/mpc85xx.h |   72 ++++++++++++++++++++++++++++++++++++
 1 files changed, 72 insertions(+), 0 deletions(-)
 create mode 100644 arch/powerpc/include/asm/mpc85xx.h

diff --git a/arch/powerpc/include/asm/mpc85xx.h b/arch/powerpc/include/asm/mpc85xx.h
new file mode 100644
index 0000000..451777c
--- /dev/null
+++ b/arch/powerpc/include/asm/mpc85xx.h
@@ -0,0 +1,72 @@
+/*
+ * MPC85xx cpu type detection
+ *
+ * Copyright 2011-2012 Freescale Semiconductor, Inc.
+ *
+ * This is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ */
+
+#ifndef __ASM_PPC_CPU_H
+#define __ASM_PPC_CPU_H
+
+#define SVR_REV(svr)	((svr) & 0xFF)		/* SOC design resision */
+#define SVR_MAJ(svr)	(((svr) >>  4) & 0xF)	/* Major revision field*/
+#define SVR_MIN(svr)	(((svr) >>  0) & 0xF)	/* Minor revision field*/
+
+/* Some parts define SVR[0:23] as the SOC version */
+#define SVR_SOC_VER(svr) (((svr) >> 8) & 0xFFFFFF)	/* SOC Version fields */
+
+#define IS_SVR_REV(svr, maj, min) \
+	((SVR_MAJ(svr) == (maj)) && (SVR_MIN(svr) == (min)))
+
+#define SVR_8533	0x803400
+#define SVR_8533_E	0x803C00
+#define SVR_8535	0x803701
+#define SVR_8535_E	0x803F01
+#define SVR_8536	0x803700
+#define SVR_8536_E	0x803F00
+#define SVR_8540	0x803000
+#define SVR_8541	0x807200
+#define SVR_8541_E	0x807A00
+#define SVR_8543	0x803200
+#define SVR_8543_E	0x803A00
+#define SVR_8544	0x803401
+#define SVR_8544_E	0x803C01
+#define SVR_8545	0x803102
+#define SVR_8545_E	0x803902
+#define SVR_8547_E	0x803901
+#define SVR_8548	0x803100
+#define SVR_8548_E	0x803900
+#define SVR_8555	0x807100
+#define SVR_8555_E	0x807900
+#define SVR_8560	0x807000
+#define SVR_8567	0x807501
+#define SVR_8567_E	0x807D01
+#define SVR_8568	0x807500
+#define SVR_8568_E	0x807D00
+#define SVR_8569	0x808000
+#define SVR_8569_E	0x808800
+#define SVR_8572	0x80E000
+#define SVR_8572_E	0x80E800
+
+
+static inline int fsl_svr_is(u32 svr)
+{
+	u32 id = SVR_SOC_VER(mfspr(SPRN_SVR));
+
+	return (id == svr);
+}
+
+/* Return true if current SOC revision is prior to (maj, min)  */
+static inline int fsl_svr_older_than(u8 maj, u8 min)
+{
+	u32 rev = SVR_REV(mfspr(SPRN_SVR));
+	u32 cmp = (maj << 4) | min;
+
+	return (rev < cmp);
+}
+
+#endif
-- 
1.6.4.1

[PATCH 2/4] fsl_pci: Add a workaround for PCI 5 errata in MPC8548

[Zhao Chenhui]

From: chenhui zhao <chenhui.zhao@freescale.com>

Issue:
As a master, the PCI IP block can combine a memory write to the last PCI double
word (4 bytes) of a cacheline with a 4 byte memory write to the first PCI double
word of the subsequent cacheline. This affects 32-bit PCI target devices that
blindly assert STOP on memory-write transactions, without detecting that the
data beat being transferred is the last data beat of the transaction. It can
cause a hang. PCI-X operation is not affected by this erratum.

Workaround:
Setting the bit MDS in the PCI Bus Function Register will disable the combining
of crossing cacheline boundary requests into one burst transaction. Therefore,
it can prevent the errata scenario from occurring.

Refer to PCI 5 in MPC8548 errata document.

Signed-off-by: Gong Chen <g.chen@freescale.com>
Signed-off-by: Zhao Chenhui <chenhui.zhao@freescale.com>
Signed-off-by: Li Yang <leoli@freescale.com>
---
 arch/powerpc/sysdev/fsl_pci.c |   20 ++++++++++++++++++++
 1 files changed, 20 insertions(+), 0 deletions(-)

diff --git a/arch/powerpc/sysdev/fsl_pci.c b/arch/powerpc/sysdev/fsl_pci.c
index 6073288..9bdee6d 100644
--- a/arch/powerpc/sysdev/fsl_pci.c
+++ b/arch/powerpc/sysdev/fsl_pci.c
@@ -31,6 +31,7 @@
 #include <asm/prom.h>
 #include <asm/pci-bridge.h>
 #include <asm/machdep.h>
+#include <asm/mpc85xx.h>
 #include <sysdev/fsl_soc.h>
 #include <sysdev/fsl_pci.h>
 
@@ -426,6 +427,7 @@ int __init fsl_add_bridge(struct device_node *dev, int is_primary)
 	struct resource rsrc;
 	const int *bus_range;
 	u8 progif;
+	u16 temp;
 
 	if (!of_device_is_available(dev)) {
 		pr_warning("%s: disabled\n", dev->full_name);
@@ -476,6 +478,24 @@ int __init fsl_add_bridge(struct device_node *dev, int is_primary)
 			PPC_INDIRECT_TYPE_SURPRESS_PRIMARY_BUS;
 		if (fsl_pcie_check_link(hose))
 			hose->indirect_type |= PPC_INDIRECT_TYPE_NO_PCIE_LINK;
+	} else {
+		/*
+		 * Set PBFR(PCI Bus Function Register)[10] = 1 to
+		 * disable the combining of crossing cacheline
+		 * boundary requests into one burst transaction.
+		 * PCI-X operation is not affected.
+		 * Fix erratum PCI 5 on MPC8548
+		 */
+#define PCI_BUS_FUNCTION 0x44
+#define PCI_BUS_FUNCTION_MDS 0x400	/* Master disable streaming */
+		if ((fsl_svr_is(SVR_8548) || fsl_svr_is(SVR_8548_E)) &&
+		    !early_find_capability(hose, 0, 0, PCI_CAP_ID_PCIX)) {
+			early_read_config_word(hose, 0, 0,
+						PCI_BUS_FUNCTION, &temp);
+			temp |= PCI_BUS_FUNCTION_MDS;
+			early_write_config_word(hose, 0, 0,
+						PCI_BUS_FUNCTION, temp);
+		}
 	}
 
 	printk(KERN_INFO "Found FSL PCI host bridge at 0x%016llx. "
-- 
1.6.4.1

Re: [PATCH 2/4] fsl_pci: Add a workaround for PCI 5 errata in MPC8548

[Kumar Gala]

On Mar 6, 2012, at 3:10 AM, Zhao Chenhui wrote:

> +		if ((fsl_svr_is(SVR_8548) || fsl_svr_is(SVR_8548_E)) &&

Should this also have 8547, 8547E, 8545, 8545E, 8543, & 8543E?

> +		    !early_find_capability(hose, 0, 0, PCI_CAP_ID_PCIX)) {
> +			early_read_config_word(hose, 0, 0,
> +						PCI_BUS_FUNCTION, &temp);
> +			temp |= PCI_BUS_FUNCTION_MDS;
> +			early_write_config_word(hose, 0, 0,
> +						PCI_BUS_FUNCTION, temp);
> +		}
> 	}

RE: [PATCH 2/4] fsl_pci: Add a workaround for PCI 5 errata in MPC8548

[Zhao Chenhui-B35336]

> On Mar 6, 2012, at 3:10 AM, Zhao Chenhui wrote:
>=20
> > +		if ((fsl_svr_is(SVR_8548) || fsl_svr_is(SVR_8548_E)) &&
>=20
> Should this also have 8547, 8547E, 8545, 8545E, 8543, & 8543E?

Yes. I will include these chips.

-Chenhui

>=20
> > +		    !early_find_capability(hose, 0, 0, PCI_CAP_ID_PCIX)) {
> > +			early_read_config_word(hose, 0, 0,
> > +						PCI_BUS_FUNCTION, &temp);
> > +			temp |=3D PCI_BUS_FUNCTION_MDS;
> > +			early_write_config_word(hose, 0, 0,
> > +						PCI_BUS_FUNCTION, temp);
> > +		}
> > 	}
>=20

[PATCH 3/4] fsl_pci: Add a workaround for PCI 6 errata in MPC8548

[Zhao Chenhui]

From: chenhui zhao <chenhui.zhao@freescale.com>

Issue:
The register bits ERR_DR[OWMSV] and ERR_DR[ORMSV] can erroneously set and
may trigger an interrupt if capturing and reporting of these events are enabled.

Workaround:
Disable OWMSV, ORMSV error capture and disable OWMSV, ORMSV error reporting.
Do not affect the functionality of the controller when the checking is disabled.

Refer to PCI 6 in MPC8548 errata document.

Signed-off-by: Zhao Chenhui <chenhui.zhao@freescale.com>
Signed-off-by: Li Yang <leoli@freescale.com>
---
 arch/powerpc/sysdev/fsl_pci.c |   16 ++++++++++++
 arch/powerpc/sysdev/fsl_pci.h |   53 ++++++++++++++++++++++++++++++++++-------
 2 files changed, 60 insertions(+), 9 deletions(-)

diff --git a/arch/powerpc/sysdev/fsl_pci.c b/arch/powerpc/sysdev/fsl_pci.c
index 9bdee6d..43aafc3 100644
--- a/arch/powerpc/sysdev/fsl_pci.c
+++ b/arch/powerpc/sysdev/fsl_pci.c
@@ -156,6 +156,22 @@ static void __init setup_pci_atmu(struct pci_controller *hose,
 	    return;
 	}
 
+	/*
+	 * PCI/PCI-X erroneous error detection
+	 * Fix erratum PCI 6 on MPC8548
+	 */
+#define OWMSV 0x10
+#define ORMSV 0x08
+	if ((fsl_svr_is(SVR_8548) || fsl_svr_is(SVR_8548_E))
+		&& fsl_svr_older_than(2, 1)) {
+		if (of_device_is_compatible(hose->dn, "fsl,mpc8540-pci")) {
+			/* disable OWMSV and ORMSV error capture */
+			setbits32(&pci->pcier.pecdr, OWMSV | ORMSV);
+			/* disable OWMSV and ORMSV error reporting */
+			clrbits32(&pci->pcier.peer, OWMSV | ORMSV);
+		}
+	}
+
 	/* Disable all windows (except powar0 since it's ignored) */
 	for(i = 1; i < 5; i++)
 		out_be32(&pci->pow[i].powar, 0);
diff --git a/arch/powerpc/sysdev/fsl_pci.h b/arch/powerpc/sysdev/fsl_pci.h
index a39ed5c..f09a78d 100644
--- a/arch/powerpc/sysdev/fsl_pci.h
+++ b/arch/powerpc/sysdev/fsl_pci.h
@@ -43,6 +43,45 @@ struct pci_inbound_window_regs {
 	u8	res2[12];
 };
 
+/* PCI Error Management Registers */
+struct pci_err_regs {
+	/*   0x.e00 - PCI Error Detect Register */
+	__be32	pedr;
+	/*   0x.e04 - PCI Error Capture Disable Register */
+	__be32	pecdr;
+	/*   0x.e08 - PCI Error Interrupt Enable Register */
+	__be32	peer;
+	/*   0x.e0c - PCI Error Attributes Capture Register */
+	__be32	peattrcr;
+	/*   0x.e10 - PCI Error Address Capture Register */
+	__be32	peaddrcr;
+	/*   0x.e14 - PCI Error Extended Address Capture Register */
+	__be32	peextaddrcr;
+	/*   0x.e18 - PCI Error Data Low Capture Register */
+	__be32	pedlcr;
+	/*   0x.e1c - PCI Error Data High Capture Register */
+	__be32	pedhcr;
+	/*   0x.e20 - PCI Gasket Timer Register */
+	__be32	gas_timr;
+	u8	res21[4];
+};
+
+/* PCI Express Error Management Registers */
+struct pcie_err_regs {
+	/*  0x.e00 - PCI/PCIE error detect register */
+	__be32	pex_err_dr;
+	u8	res21[4];
+	/*  0x.e08 - PCI/PCIE error interrupt enable register */
+	__be32	pex_err_en;
+	u8	res22[4];
+	/*  0x.e10 - PCI/PCIE error disable register */
+	__be32	pex_err_disr;
+	u8	res23[12];
+	/*  0x.e20 - PCI/PCIE error capture status register */
+	__be32	pex_err_cap_stat;
+	u8	res24[4];
+};
+
 /* PCI/PCI Express IO block registers for 85xx/86xx */
 struct ccsr_pci {
 	__be32	config_addr;		/* 0x.000 - PCI/PCIE Configuration Address Register */
@@ -73,15 +112,11 @@ struct ccsr_pci {
  * define an inbound window base extended address register.
  */
 	struct pci_inbound_window_regs piw[4];
-
-	__be32	pex_err_dr;		/* 0x.e00 - PCI/PCIE error detect register */
-	u8	res21[4];
-	__be32	pex_err_en;		/* 0x.e08 - PCI/PCIE error interrupt enable register */
-	u8	res22[4];
-	__be32	pex_err_disr;		/* 0x.e10 - PCI/PCIE error disable register */
-	u8	res23[12];
-	__be32	pex_err_cap_stat;	/* 0x.e20 - PCI/PCIE error capture status register */
-	u8	res24[4];
+/* PCI/PCI Express Error Management Registers */
+	union {
+		struct pci_err_regs pcier;
+		struct pcie_err_regs pexer;
+	};
 	__be32	pex_err_cap_r0;		/* 0x.e28 - PCIE error capture register 0 */
 	__be32	pex_err_cap_r1;		/* 0x.e2c - PCIE error capture register 0 */
 	__be32	pex_err_cap_r2;		/* 0x.e30 - PCIE error capture register 0 */
-- 
1.6.4.1

[PATCH 4/4] powerpc/mpc8548: Add workaround for erratum NMG_SRIO135

[Zhao Chenhui]

From: chenhui zhao <chenhui.zhao@freescale.com>

Issue:
Applications using lwarx/stwcx instructions in the core to
compete for a software lock or semaphore with a device on
RapidIO using read atomic set, clr, inc, or dec in a similar
manner may falsely result in both masters seeing the lock
as "available". This could result in data corruption as
both masters try to modify the same piece of data protected
by the lock.

Workaround:
Set bits 13 and 29 of CCSR offset 0x01010 (EEBPCR register
of the ECM) during initialization and leave them set
indefinitely. This may slightly degrade overall system
performance.

Refer to SRIO39 in MPC8548 errata document.

Signed-off-by: Gong Chen <g.chen@freescale.com>
Signed-off-by: Zhao Chenhui <chenhui.zhao@freescale.com>
Signed-off-by: Li Yang <leoli@freescale.com>
---
 arch/powerpc/sysdev/fsl_rio.c |   44 +++++++++++++++++++++++++++++++++++++++++
 1 files changed, 44 insertions(+), 0 deletions(-)

diff --git a/arch/powerpc/sysdev/fsl_rio.c b/arch/powerpc/sysdev/fsl_rio.c
index a4c4f4a..78a0c3d 100644
--- a/arch/powerpc/sysdev/fsl_rio.c
+++ b/arch/powerpc/sysdev/fsl_rio.c
@@ -35,6 +35,8 @@
 #include <linux/io.h>
 #include <linux/uaccess.h>
 #include <asm/machdep.h>
+#include <asm/mpc85xx.h>
+#include <sysdev/fsl_soc.h>
 
 #include "fsl_rio.h"
 
@@ -321,6 +323,37 @@ static inline void fsl_rio_info(struct device *dev, u32 ccsr)
 	}
 }
 
+#define CCSR_ECM_EEBPCR_OFF 0x10
+/*
+ * fixup_erratum_srio135 - Fix Serial RapidIO atomic operation erratum
+ */
+static int fixup_erratum_srio135(struct device *dev)
+{
+	struct device_node *np;
+	void __iomem *ecm;
+
+	np = of_find_compatible_node(NULL, NULL, "fsl,mpc8548-ecm");
+	if (!np) {
+		dev_err(dev, "no ECM node found.\n");
+		return -ENODEV;
+	}
+
+	ecm = of_iomap(np, 0);
+	of_node_put(np);
+	if (!ecm) {
+		dev_err(dev, "failed to map ECM register base.\n");
+		return -ENODEV;
+	}
+	/*
+	 * Set bits 13 and 29 of the EEBPCR register in the ECM
+	 * during initialization and leave them set indefinitely.
+	 */
+	setbits32(ecm + CCSR_ECM_EEBPCR_OFF, 0x00040004);
+	iounmap(ecm);
+
+	return 0;
+}
+
 /**
  * fsl_rio_setup - Setup Freescale PowerPC RapidIO interface
  * @dev: platform_device pointer
@@ -358,6 +391,17 @@ int fsl_rio_setup(struct platform_device *dev)
 				dev->dev.of_node->full_name);
 		return -EFAULT;
 	}
+
+	/* Fix erratum NMG_SRIO135 */
+	if (fsl_svr_is(SVR_8548) || fsl_svr_is(SVR_8548_E)) {
+		rc = fixup_erratum_srio135(&dev->dev);
+		if (rc) {
+			dev_err(&dev->dev,
+				"Failed to fix the erratum NMG_SRIO135.");
+			return rc;
+		}
+	}
+
 	dev_info(&dev->dev, "Of-device full name %s\n",
 			dev->dev.of_node->full_name);
 	dev_info(&dev->dev, "Regs: %pR\n", &regs);
-- 
1.6.4.1

RE: [PATCH 4/4] powerpc/mpc8548: Add workaround for erratum NMG_SRIO135

[David Laight]

=20
> Issue:
> Applications using lwarx/stwcx instructions in the core to
> compete for a software lock or semaphore with a device on
> RapidIO using read atomic set, clr, inc, or dec in a similar
> manner may falsely result in both masters seeing the lock
> as "available". This could result in data corruption as
> both masters try to modify the same piece of data protected
> by the lock.
>=20
> Workaround:
> Set bits 13 and 29 of CCSR offset 0x01010 (EEBPCR register
> of the ECM) during initialization and leave them set
> indefinitely. This may slightly degrade overall system
> performance.

Might be worth actually saying what these bits do, and
why/when overall performance is affected.

Is the problem trying to do locked read-write cycles
on a slow peripheral bus?
Might be a case for just 'not doing that'.

	David

Re: [4/4] powerpc/mpc8548: Add workaround for erratum NMG_SRIO135

[Scott Wood]

On Tue, Mar 06, 2012 at 05:10:56PM +0800, chenhui zhao wrote:
> From: chenhui zhao <chenhui.zhao@freescale.com>
> 
> Issue:
> Applications using lwarx/stwcx instructions in the core to
> compete for a software lock or semaphore with a device on
> RapidIO using read atomic set, clr, inc, or dec in a similar
> manner may falsely result in both masters seeing the lock
> as "available". This could result in data corruption as
> both masters try to modify the same piece of data protected
> by the lock.
> 
> Workaround:
> Set bits 13 and 29 of CCSR offset 0x01010 (EEBPCR register
> of the ECM) during initialization and leave them set
> indefinitely. This may slightly degrade overall system
> performance.
> 
> Refer to SRIO39 in MPC8548 errata document.
> 
> Signed-off-by: Gong Chen <g.chen@freescale.com>
> Signed-off-by: Zhao Chenhui <chenhui.zhao@freescale.com>
> Signed-off-by: Li Yang <leoli@freescale.com>
> 
> ---
> arch/powerpc/sysdev/fsl_rio.c |   44 +++++++++++++++++++++++++++++++++++++++++
>  1 files changed, 44 insertions(+), 0 deletions(-)
[snip]
> @@ -358,6 +391,17 @@ int fsl_rio_setup(struct platform_device *dev)
>  				dev->dev.of_node->full_name);
>  		return -EFAULT;
>  	}
> +
> +	/* Fix erratum NMG_SRIO135 */
> +	if (fsl_svr_is(SVR_8548) || fsl_svr_is(SVR_8548_E)) {
> +		rc = fixup_erratum_srio135(&dev->dev);
> +		if (rc) {
> +			dev_err(&dev->dev,
> +				"Failed to fix the erratum NMG_SRIO135.");
> +			return rc;
> +		}
> +	}

This needs to be respun based on the current tree.

-Scott

RE: [4/4] powerpc/mpc8548: Add workaround for erratum NMG_SRIO135

[Zhao Chenhui-B35336]

=0A=
OK. I will do.=0A=
=0A=
-Chenhui=0A=
=0A=
________________________________________=0A=
From: Wood Scott-B07421=0A=
Sent: Thursday, October 17, 2013 7:20=0A=
To: Zhao Chenhui-B35336=0A=
Cc: linuxppc-dev@lists.ozlabs.org=0A=
Subject: Re: [4/4] powerpc/mpc8548: Add workaround for erratum NMG_SRIO135=
=0A=
=0A=
On Tue, Mar 06, 2012 at 05:10:56PM +0800, chenhui zhao wrote:=0A=
> From: chenhui zhao <chenhui.zhao@freescale.com>=0A=
>=0A=
> Issue:=0A=
> Applications using lwarx/stwcx instructions in the core to=0A=
> compete for a software lock or semaphore with a device on=0A=
> RapidIO using read atomic set, clr, inc, or dec in a similar=0A=
> manner may falsely result in both masters seeing the lock=0A=
> as "available". This could result in data corruption as=0A=
> both masters try to modify the same piece of data protected=0A=
> by the lock.=0A=
>=0A=
> Workaround:=0A=
> Set bits 13 and 29 of CCSR offset 0x01010 (EEBPCR register=0A=
> of the ECM) during initialization and leave them set=0A=
> indefinitely. This may slightly degrade overall system=0A=
> performance.=0A=
>=0A=
> Refer to SRIO39 in MPC8548 errata document.=0A=
>=0A=
> Signed-off-by: Gong Chen <g.chen@freescale.com>=0A=
> Signed-off-by: Zhao Chenhui <chenhui.zhao@freescale.com>=0A=
> Signed-off-by: Li Yang <leoli@freescale.com>=0A=
>=0A=
> ---=0A=
> arch/powerpc/sysdev/fsl_rio.c |   44 ++++++++++++++++++++++++++++++++++++=
+++++=0A=
>  1 files changed, 44 insertions(+), 0 deletions(-)=0A=
[snip]=0A=
> @@ -358,6 +391,17 @@ int fsl_rio_setup(struct platform_device *dev)=0A=
>                               dev->dev.of_node->full_name);=0A=
>               return -EFAULT;=0A=
>       }=0A=
> +=0A=
> +     /* Fix erratum NMG_SRIO135 */=0A=
> +     if (fsl_svr_is(SVR_8548) || fsl_svr_is(SVR_8548_E)) {=0A=
> +             rc =3D fixup_erratum_srio135(&dev->dev);=0A=
> +             if (rc) {=0A=
> +                     dev_err(&dev->dev,=0A=
> +                             "Failed to fix the erratum NMG_SRIO135.");=
=0A=
> +                     return rc;=0A=
> +             }=0A=
> +     }=0A=
=0A=
This needs to be respun based on the current tree.=0A=
=0A=
-Scott=0A=

Re: [1/4] powerpc/85xx: Add a head file for cpu type detection

[Scott Wood]

On Mon, Mar 05, 2012 at 11:10:53PM -0000, chenhui zhao wrote:
> From: chenhui zhao <chenhui.zhao@freescale.com>
> 
> The workarounds need to detect the cpu type. Add these macros
> and inline routines to help cpu type detection in runtime.
> 
> Signed-off-by: Zhao Chenhui <chenhui.zhao@freescale.com>
> Signed-off-by: Li Yang <leoli@freescale.com>
> 
> ---
> arch/powerpc/include/asm/mpc85xx.h |   72 ++++++++++++++++++++++++++++++++++++
>  1 files changed, 72 insertions(+), 0 deletions(-)
>  create mode 100644 arch/powerpc/include/asm/mpc85xx.h
> 
> diff --git a/arch/powerpc/include/asm/mpc85xx.h b/arch/powerpc/include/asm/mpc85xx.h
> new file mode 100644
> index 0000000..451777c
> --- /dev/null
> +++ b/arch/powerpc/include/asm/mpc85xx.h
> @@ -0,0 +1,72 @@
> +/*
> + * MPC85xx cpu type detection
> + *
> + * Copyright 2011-2012 Freescale Semiconductor, Inc.
> + *
> + * This is free software; you can redistribute it and/or modify
> + * it under the terms of the GNU General Public License as published by
> + * the Free Software Foundation; either version 2 of the License, or
> + * (at your option) any later version.
> + */
> +
> +#ifndef __ASM_PPC_CPU_H
> +#define __ASM_PPC_CPU_H

s/CPU/MPC85xx/

> +#define SVR_REV(svr)	((svr) & 0xFF)		/* SOC design resision */

Please update U-Boot's definition, so that shared code doesn't run into
problems.

> +#define SVR_MAJ(svr)	(((svr) >>  4) & 0xF)	/* Major revision field*/
> +#define SVR_MIN(svr)	(((svr) >>  0) & 0xF)	/* Minor revision field*/
> +
> +/* Some parts define SVR[0:23] as the SOC version */
> +#define SVR_SOC_VER(svr) (((svr) >> 8) & 0xFFFFFF)	/* SOC Version fields */
> +
> +#define IS_SVR_REV(svr, maj, min) \
> +	((SVR_MAJ(svr) == (maj)) && (SVR_MIN(svr) == (min)))
> +
> +#define SVR_8533	0x803400
> +#define SVR_8533_E	0x803C00
> +#define SVR_8535	0x803701
> +#define SVR_8535_E	0x803F01
> +#define SVR_8536	0x803700
> +#define SVR_8536_E	0x803F00
> +#define SVR_8540	0x803000
> +#define SVR_8541	0x807200
> +#define SVR_8541_E	0x807A00
> +#define SVR_8543	0x803200
> +#define SVR_8543_E	0x803A00

Can we separate out E as an orthogonal bit, as we now do in U-Boot?

> +#define SVR_8544	0x803401
> +#define SVR_8544_E	0x803C01
> +#define SVR_8545	0x803102
> +#define SVR_8545_E	0x803902
> +#define SVR_8547_E	0x803901
> +#define SVR_8548	0x803100
> +#define SVR_8548_E	0x803900
> +#define SVR_8555	0x807100
> +#define SVR_8555_E	0x807900
> +#define SVR_8560	0x807000
> +#define SVR_8567	0x807501
> +#define SVR_8567_E	0x807D01
> +#define SVR_8568	0x807500
> +#define SVR_8568_E	0x807D00
> +#define SVR_8569	0x808000
> +#define SVR_8569_E	0x808800
> +#define SVR_8572	0x80E000
> +#define SVR_8572_E	0x80E800
> +
> +
> +static inline int fsl_svr_is(u32 svr)
> +{
> +	u32 id = SVR_SOC_VER(mfspr(SPRN_SVR));
> +
> +	return (id == svr);
> +}

fsl_svr_is() and IS_SVR_REV() are confusingly similar, and the
upper/lower difference and word-order difference is jarring.  I'm not
sure why you even need fsl_svr_is.  This file is obviously patterned
after U-Boot code, but U-Boot doesn't have this.  Why can't the caller do
the equality check?

> +/* Return true if current SOC revision is prior to (maj, min)  */
> +static inline int fsl_svr_older_than(u8 maj, u8 min)
> +{
> +	u32 rev = SVR_REV(mfspr(SPRN_SVR));
> +	u32 cmp = (maj << 4) | min;
> +
> +	return (rev < cmp);
> +}

Is this that much easier than the caller doing:

	if (SVR_REV(svr) < 0x20)

?

-Scott