From: Sebastian Andrzej Siewior <bigeasy@linutronix.de>
To: linuxppc-dev@lists.ozlabs.org
Cc: Sebastian Andrzej Siewior <bigeasy@linutronix.de>
Subject: [PATCH 1/2] powerpc/p2020rdb: move the NAND address.
Date: Thu, 15 Mar 2012 18:40:27 +0100 [thread overview]
Message-ID: <1331833228-14903-1-git-send-email-bigeasy@linutronix.de> (raw)
It is not at 0xffa00000. According to current u-boot source the NAND
controller is always at 0xff800000 and it is either at CS0 or CS1
depending on NAND or NAND+NOR mode. In 36bit mode it is shifted to
0xfff800000 but it has always an eight there and never an A.
Signed-off-by: Sebastian Andrzej Siewior <bigeasy@linutronix.de>
---
arch/powerpc/boot/dts/p2020rdb.dts | 2 +-
1 files changed, 1 insertions(+), 1 deletions(-)
diff --git a/arch/powerpc/boot/dts/p2020rdb.dts b/arch/powerpc/boot/dts/p2020rdb.dts
index eb8a6aa..8f25ef2 100644
--- a/arch/powerpc/boot/dts/p2020rdb.dts
+++ b/arch/powerpc/boot/dts/p2020rdb.dts
@@ -34,7 +34,7 @@
/* NOR and NAND Flashes */
ranges = <0x0 0x0 0x0 0xef000000 0x01000000
- 0x1 0x0 0x0 0xffa00000 0x00040000
+ 0x1 0x0 0x0 0xff800000 0x00040000
0x2 0x0 0x0 0xffb00000 0x00020000>;
nor@0,0 {
--
1.7.9.1
next reply other threads:[~2012-03-15 17:39 UTC|newest]
Thread overview: 4+ messages / expand[flat|nested] mbox.gz Atom feed top
2012-03-15 17:40 Sebastian Andrzej Siewior [this message]
2012-03-15 17:40 ` [PATCH 2/2] powerpc/p2020rdb p1010rdb: lower spi flash freq to 40Mhz Sebastian Andrzej Siewior
2012-03-16 15:13 ` Kumar Gala
2012-03-16 15:13 ` [PATCH 1/2] powerpc/p2020rdb: move the NAND address Kumar Gala
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