From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from gate.crashing.org (gate.crashing.org [63.228.1.57]) (using TLSv1 with cipher DHE-RSA-AES256-SHA (256/256 bits)) (Client did not present a certificate) by ozlabs.org (Postfix) with ESMTPS id 4CCCAB6FB6 for ; Wed, 27 Jun 2012 08:10:21 +1000 (EST) Message-ID: <1340748603.3732.26.camel@pasglop> Subject: Re: [PATCH v6 1/5] powerpc/85xx: implement hardware timebase sync From: Benjamin Herrenschmidt To: Scott Wood Date: Wed, 27 Jun 2012 08:10:03 +1000 In-Reply-To: <4FEA2D93.3030002@freescale.com> References: <1340706359-9455-1-git-send-email-chenhui.zhao@freescale.com> <4FEA2D93.3030002@freescale.com> Content-Type: text/plain; charset="UTF-8" Mime-Version: 1.0 Cc: linux-kernel@vger.kernel.org, linuxppc-dev@lists.ozlabs.org, Zhao Chenhui List-Id: Linux on PowerPC Developers Mail List List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , On Tue, 2012-06-26 at 16:45 -0500, Scott Wood wrote: > Some parts are due to corenet versus non-corenet, such as the actual > register you write to to disable/enable the timebase. > > There's also a two-core assumption in the synchronization code which > I've complained about multiple times -- although on closer inspection it > looks like this is done under cpu_add_remove_lock, and we can assume > that there's only one core at a time in take_timebase(), regardless of > how many cores are in the system. Right, it should work fine with any number of cores or am I missing something ? (btw, since when complaining about something helps ? :-) Cheers, Ben.