From: "Aneesh Kumar K.V" <aneesh.kumar@linux.vnet.ibm.com>
To: benh@kernel.crashing.org, paulus@samba.org
Cc: linuxppc-dev@lists.ozlabs.org,
"Aneesh Kumar K.V" <aneesh.kumar@linux.vnet.ibm.com>
Subject: [PATCH -V4 11/12] arch/powerpc: properly offset the context bits for 1T segemnts
Date: Wed, 25 Jul 2012 18:28:04 +0530 [thread overview]
Message-ID: <1343221085-30661-12-git-send-email-aneesh.kumar@linux.vnet.ibm.com> (raw)
In-Reply-To: <1343221085-30661-1-git-send-email-aneesh.kumar@linux.vnet.ibm.com>
From: "Aneesh Kumar K.V" <aneesh.kumar@linux.vnet.ibm.com>
We should do rldimi r10,r9,USER_ESID_BITS,0 only after populating
r10 with ESID bits.
Signed-off-by: Aneesh Kumar K.V <aneesh.kumar@linux.vnet.ibm.com>
---
arch/powerpc/mm/slb_low.S | 12 ++++++++----
1 file changed, 8 insertions(+), 4 deletions(-)
diff --git a/arch/powerpc/mm/slb_low.S b/arch/powerpc/mm/slb_low.S
index db2cb3f..7bd8438 100644
--- a/arch/powerpc/mm/slb_low.S
+++ b/arch/powerpc/mm/slb_low.S
@@ -59,6 +59,7 @@ _GLOBAL(slb_miss_kernel_load_linear)
BEGIN_FTR_SECTION
b slb_finish_load
END_MMU_FTR_SECTION_IFCLR(MMU_FTR_1T_SEGMENT)
+ srdi r10,r10,40-28 /* get 1T ESID */
b slb_finish_load_1T
1:
@@ -88,6 +89,7 @@ _GLOBAL(slb_miss_kernel_load_vmemmap)
BEGIN_FTR_SECTION
b slb_finish_load
END_MMU_FTR_SECTION_IFCLR(MMU_FTR_1T_SEGMENT)
+ srdi r10,r10,40-28 /* get 1T ESID */
b slb_finish_load_1T
0: /* user address: proto-VSID = context << 15 | ESID. First check
@@ -155,13 +157,16 @@ END_MMU_FTR_SECTION_IFCLR(MMU_FTR_1T_SEGMENT)
ld r9,PACACONTEXTID(r13)
BEGIN_FTR_SECTION
cmpldi r10,0x1000
+ bge 9f
END_MMU_FTR_SECTION_IFSET(MMU_FTR_1T_SEGMENT)
rldimi r10,r9,USER_ESID_BITS,0
+ b slb_finish_load
BEGIN_FTR_SECTION
- bge slb_finish_load_1T
+9:
+ srdi r10,r10,40-28 /* get 1T ESID */
+ rldimi r10,r9,USER_ESID_BITS,0
+ b slb_finish_load_1T
END_MMU_FTR_SECTION_IFSET(MMU_FTR_1T_SEGMENT)
- b slb_finish_load
-
8: /* invalid EA */
li r10,0 /* BAD_VSID */
li r11,SLB_VSID_USER /* flags don't much matter */
@@ -292,7 +297,6 @@ _GLOBAL(slb_compare_rr_to_size)
* r3 = EA, r10 = proto-VSID, r11 = flags, clobbers r9
*/
slb_finish_load_1T:
- srdi r10,r10,40-28 /* get 1T ESID */
ASM_VSID_SCRAMBLE(r10,r9,1T)
/*
* bits above VSID_BITS_1T need to be ignored from r10
--
1.7.10
next prev parent reply other threads:[~2012-07-25 12:58 UTC|newest]
Thread overview: 16+ messages / expand[flat|nested] mbox.gz Atom feed top
2012-07-25 12:57 [PATCH -V4 0/12] arch/powerpc: Add 64TB support to ppc64 Aneesh Kumar K.V
2012-07-25 12:57 ` [PATCH -V4 01/12] arch/powerpc: Use hpt_va to compute virtual address Aneesh Kumar K.V
2012-07-25 12:57 ` [PATCH -V4 02/12] arch/powerpc: Simplify hpte_decode Aneesh Kumar K.V
2012-07-25 12:57 ` [PATCH -V4 03/12] arch/powerpc: Convert virtual address to vpn Aneesh Kumar K.V
2012-07-25 12:57 ` [PATCH -V4 04/12] arch/powerpc: Rename va " Aneesh Kumar K.V
2012-07-25 12:57 ` [PATCH -V4 05/12] arch/powerpc: Make KERN_VIRT_SIZE not dependend on PGTABLE_RANGE Aneesh Kumar K.V
2012-07-25 12:57 ` [PATCH -V4 06/12] arch/powerpc: Increase the slice range to 64TB Aneesh Kumar K.V
2012-07-25 12:58 ` [PATCH -V4 07/12] arch/powerpc: Make some of the PGTABLE_RANGE dependency explicit Aneesh Kumar K.V
2012-07-25 12:58 ` [PATCH -V4 08/12] arch/powerpc: Use the rquired number of VSID bits in slbmte Aneesh Kumar K.V
2012-07-25 12:58 ` [PATCH -V4 09/12] arch/powerpc: Use 32bit array for slb cache Aneesh Kumar K.V
2012-07-25 12:58 ` [PATCH -V4 10/12] arch/powerpc: Add 64TB support Aneesh Kumar K.V
2012-07-25 12:58 ` Aneesh Kumar K.V [this message]
2012-07-30 0:58 ` [PATCH -V4 11/12] arch/powerpc: properly offset the context bits for 1T segemnts Paul Mackerras
2012-07-30 5:36 ` Aneesh Kumar K.V
2012-07-25 12:58 ` [PATCH -V4 12/12] arch/powerpc: properly isolate kernel and user proto-VSID Aneesh Kumar K.V
2012-07-25 15:21 ` Aneesh Kumar K.V
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