[PATCH v2 2/2] powerpc/mpic: add global timer support

[PATCH v2 2/2] powerpc/mpic: add global timer support

[Dongsheng.wang]

From: Wang Dongsheng <Dongsheng.Wang@freescale.com>

The MPIC global timer is a hardware timer inside the Freescale PIC comply
to Open-PIC standard. When the timer is timeout of the specified interval,
the hardware timer generates an interrupt. The driver currently is only
tested on fsl chip, but it can potentially support other global timers
complying to Open-PIC standard.
The two independent groups of global timer on fsl chip, group A and group B,
are identical in their functionality, except that they appear at different
locations within the PIC register map. The hardware timer can be cascaded to
create timers larger than the default 31-bit global timers. Timer cascade
fields allow configuration of up to two 63-bit timers. But These two groups
of timers cannot be cascaded together.
It can be used as a wakeup source for low power modes. It also could be used
as periodical timer for protocols, drivers and etc.

Signed-off-by: Wang Dongsheng <Dongsheng.Wang@freescale.com>
Signed-off-by: Li Yang <leoli@freescale.com>
---
 arch/powerpc/include/asm/mpic_timer.h |   15 +
 arch/powerpc/platforms/Kconfig        |    5 +
 arch/powerpc/sysdev/Makefile          |    1 +
 arch/powerpc/sysdev/mpic_timer.c      |  525 +++++++++++++++++++++++++++++++++
 4 files changed, 546 insertions(+), 0 deletions(-)
 create mode 100644 arch/powerpc/include/asm/mpic_timer.h
 create mode 100644 arch/powerpc/sysdev/mpic_timer.c

diff --git a/arch/powerpc/include/asm/mpic_timer.h b/arch/powerpc/include/asm/mpic_timer.h
new file mode 100644
index 0000000..01d58a2
--- /dev/null
+++ b/arch/powerpc/include/asm/mpic_timer.h
@@ -0,0 +1,15 @@
+#ifndef __MPIC_TIMER__
+#define __MPIC_TIMER__
+
+#include <linux/interrupt.h>
+#include <linux/time.h>
+
+struct mpic_timer *mpic_request_timer(irq_handler_t fn,  void *dev,
+		const struct timeval *time);
+
+void mpic_start_timer(struct mpic_timer *handle);
+
+void mpic_stop_timer(struct mpic_timer *handle);
+
+void mpic_free_timer(struct mpic_timer *handle);
+#endif
diff --git a/arch/powerpc/platforms/Kconfig b/arch/powerpc/platforms/Kconfig
index e7a896a..d82a822 100644
--- a/arch/powerpc/platforms/Kconfig
+++ b/arch/powerpc/platforms/Kconfig
@@ -87,6 +87,11 @@ config MPIC
 	bool
 	default n
 
+config MPIC_TIMER
+	bool "MPIC Global Timer"
+	depends on MPIC && FSL_SOC
+	default n
+
 config PPC_EPAPR_HV_PIC
 	bool
 	default n
diff --git a/arch/powerpc/sysdev/Makefile b/arch/powerpc/sysdev/Makefile
index 1bd7ecb..b1a9e4d 100644
--- a/arch/powerpc/sysdev/Makefile
+++ b/arch/powerpc/sysdev/Makefile
@@ -6,6 +6,7 @@ mpic-msi-obj-$(CONFIG_PCI_MSI)	+= mpic_msi.o mpic_u3msi.o mpic_pasemi_msi.o
 obj-$(CONFIG_MPIC)		+= mpic.o $(mpic-msi-obj-y)
 mpic-msgr-obj-$(CONFIG_MPIC_MSGR)	+= mpic_msgr.o
 obj-$(CONFIG_MPIC)		+= mpic.o $(mpic-msi-obj-y) $(mpic-msgr-obj-y)
+obj-$(CONFIG_MPIC_TIMER)	+= mpic_timer.o
 obj-$(CONFIG_PPC_EPAPR_HV_PIC)	+= ehv_pic.o
 fsl-msi-obj-$(CONFIG_PCI_MSI)	+= fsl_msi.o
 obj-$(CONFIG_PPC_MSI_BITMAP)	+= msi_bitmap.o
diff --git a/arch/powerpc/sysdev/mpic_timer.c b/arch/powerpc/sysdev/mpic_timer.c
new file mode 100644
index 0000000..1b3ee59
--- /dev/null
+++ b/arch/powerpc/sysdev/mpic_timer.c
@@ -0,0 +1,525 @@
+/*
+ * Copyright (c) 2012 Freescale Semiconductor, Inc. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License version 2 as published
+ * by the Free Software Foundation.
+ */
+
+#include <linux/kernel.h>
+#include <linux/init.h>
+#include <linux/module.h>
+#include <linux/errno.h>
+#include <asm/io.h>
+#include <linux/mm.h>
+#include <linux/interrupt.h>
+#include <linux/slab.h>
+#include <linux/of.h>
+#include <linux/of_device.h>
+
+#include <sysdev/fsl_soc.h>
+#include <asm/mpic_timer.h>
+
+#define FSL_GLOBAL_TIMER		0x1
+
+#define MPIC_TIMER_TCR_CLKDIV_64	0x00000300
+#define MPIC_TIMER_TCR_ROVR_OFFSET	24
+
+#define TIMER_STOP			0x80000000
+#define ALL_TIMER			4
+#define MAX_TICKS			(~0U>>1)
+#define MAX_TICKS_CASCADE		(~0U)
+#define TIMER_OFFSET(num)		(1 << (ALL_TIMER - 1 - num))
+#define ONE_SECOND			1000000
+
+struct timer_regs {
+	u32	gtccr;
+	u32	res0[3];
+	u32	gtbcr;
+	u32	res1[3];
+	u32	gtvpr;
+	u32	res2[3];
+	u32	gtdr;
+	u32	res3[3];
+};
+
+struct cascade_priv {
+	u32 tcr_value;			/* TCR register: CASC & ROVR value */
+	unsigned int cascade_map;	/* cascade map */
+	unsigned int timer_num;		/* cascade control timer */
+};
+
+struct mpic_timer {
+	void			*dev;
+	struct cascade_priv	*cascade_handle;
+	unsigned int		num;
+	int			irq;
+};
+
+struct group_priv {
+	struct timer_regs __iomem	*regs;
+	struct mpic_timer		timer[ALL_TIMER];
+	struct list_head		node;
+	unsigned int			timerfreq;
+	unsigned int			idle;
+	unsigned int			flags;
+	spinlock_t			lock;
+	void __iomem			*group_tcr;
+	void __iomem			*group_tfrr;
+};
+
+static struct cascade_priv cascade_timer[] = {
+	/* cascade timer 0 and 1 */
+	{0x1, 0xc, 0x1},
+	/* cascade timer 1 and 2 */
+	{0x2, 0x6, 0x2},
+	/* cascade timer 2 and 3 */
+	{0x4, 0x3, 0x3}
+};
+
+static u32 ccbfreq;
+static LIST_HEAD(group_list);
+
+/* the time set by the user is converted to "ticks" */
+static int transform_time(struct group_priv *priv, const struct timeval *time,
+		u64 *ticks)
+{
+	u64 max_value;		/* prevent u64 overflow */
+	u64 tmp = 0;
+
+	u64 tmp_sec = 0;
+	u64 tmp_ms = 0;
+	u64 tmp_us = 0;
+	u32 div = 0;
+
+	if (priv->flags & FSL_GLOBAL_TIMER)
+		max_value = div_u64(ULLONG_MAX, ccbfreq);
+	else
+		max_value = div_u64(ULLONG_MAX, priv->timerfreq);
+
+	if (time->tv_sec > max_value ||
+			(time->tv_sec == max_value && time->tv_usec > 0))
+		return -EINVAL;
+
+	if (!(priv->flags & FSL_GLOBAL_TIMER)) {
+		tmp = time->tv_sec * priv->timerfreq;
+		*ticks = tmp;
+
+		return 0;
+	}
+
+	div = (1 << (MPIC_TIMER_TCR_CLKDIV_64 >> 8)) * 8;
+
+	tmp_sec = div_u64((u64)time->tv_sec * (u64)ccbfreq, div);
+	tmp += tmp_sec;
+
+	tmp_ms = time->tv_usec / 1000;
+	tmp_ms = div_u64((u64)tmp_ms * (u64)ccbfreq, div * 1000);
+	tmp += tmp_ms;
+
+	tmp_us = time->tv_usec % 1000;
+	tmp_us = div_u64((u64)tmp_us * (u64)ccbfreq, div * 1000000);
+	tmp += tmp_us;
+
+	*ticks = tmp;
+
+	return 0;
+}
+
+/* detect whether there is a cascade timer available */
+static struct mpic_timer *detect_idle_cascade_timer(struct group_priv *priv)
+{
+	struct cascade_priv *casc_priv;
+	unsigned int tmp;
+	unsigned int array_size = ARRAY_SIZE(cascade_timer);
+	unsigned int num;
+	unsigned int i;
+	unsigned long flags;
+
+	casc_priv = cascade_timer;
+	for (i = 0; i < array_size; i++) {
+		spin_lock_irqsave(&priv->lock, flags);
+		tmp = casc_priv->cascade_map & priv->idle;
+		if (tmp == casc_priv->cascade_map) {
+			num = casc_priv->timer_num;
+			priv->timer[num].cascade_handle = casc_priv;
+
+			/* set timer busy */
+			priv->idle &= ~casc_priv->cascade_map;
+			spin_unlock_irqrestore(&priv->lock, flags);
+			return &priv->timer[num];
+		}
+		spin_unlock_irqrestore(&priv->lock, flags);
+		casc_priv++;
+	}
+
+	return NULL;
+}
+
+static int set_cascade_timer(struct group_priv *priv, u64 ticks,
+		unsigned int num)
+{
+	struct cascade_priv *casc_priv;
+	u32 tmp;
+	u32 tmp_ticks;
+	u32 rem_ticks;
+
+	/* set group tcr reg for cascade */
+	casc_priv = priv->timer[num].cascade_handle;
+	if (!casc_priv)
+		return -EINVAL;
+
+	tmp = casc_priv->tcr_value |
+		(casc_priv->tcr_value << MPIC_TIMER_TCR_ROVR_OFFSET);
+	setbits32(priv->group_tcr, tmp);
+
+	tmp_ticks = div_u64_rem(ticks, MAX_TICKS_CASCADE, &rem_ticks);
+
+	out_be32(&priv->regs[num].gtccr, 0);
+	out_be32(&priv->regs[num].gtbcr, tmp_ticks | TIMER_STOP);
+
+	out_be32(&priv->regs[num - 1].gtccr, 0);
+	out_be32(&priv->regs[num - 1].gtbcr, rem_ticks);
+
+	return 0;
+}
+
+static struct mpic_timer *get_cascade_timer(struct group_priv *priv, u64 ticks)
+{
+	struct mpic_timer *allocated_timer = NULL;
+
+	/* Two cascade timers: Support the maximum time */
+	const u64 max_ticks = (u64)MAX_TICKS * (u64)MAX_TICKS_CASCADE;
+	int ret;
+
+	if (ticks > max_ticks)
+		return NULL;
+
+	/* detect idle timer */
+	allocated_timer = detect_idle_cascade_timer(priv);
+	if (!allocated_timer)
+		return NULL;
+
+	/* set ticks to timer */
+	ret = set_cascade_timer(priv, ticks, allocated_timer->num);
+	if (ret < 0)
+		return NULL;
+
+	return allocated_timer;
+}
+
+static struct mpic_timer *get_timer(const struct timeval *time)
+{
+	struct group_priv *priv;
+	struct mpic_timer *timer = NULL;
+
+	u64 ticks = 0;
+	unsigned int num;
+	unsigned int i;
+	unsigned long flags;
+	int ret = 0;
+
+	list_for_each_entry(priv, &group_list, node) {
+		ret = transform_time(priv, time, &ticks);
+		if (ret < 0)
+			return NULL;
+
+		if (ticks > MAX_TICKS) {
+			if (!(priv->flags & FSL_GLOBAL_TIMER))
+				return NULL;
+
+			timer = get_cascade_timer(priv, ticks);
+			if (!timer)
+				continue;
+			else
+				return timer;
+		}
+
+		for (i = 0; i < ALL_TIMER; i++) {
+			/* one timer: Reverse allocation */
+			num = ALL_TIMER - 1 - i;
+			spin_lock_irqsave(&priv->lock, flags);
+			if (priv->idle & (1 << i)) {
+				/* set timer busy */
+				priv->idle &= ~(1 << i);
+				/* set ticks & stop timer */
+				out_be32(&priv->regs[num].gtbcr,
+					ticks | TIMER_STOP);
+				out_be32(&priv->regs[num].gtccr, 0);
+				priv->timer[num].cascade_handle = NULL;
+				spin_unlock_irqrestore(&priv->lock, flags);
+				return &priv->timer[num];
+			}
+			spin_unlock_irqrestore(&priv->lock, flags);
+		}
+	}
+
+	return NULL;
+}
+
+/**
+ * mpic_request_timer - get a hardware timer
+ * @fn: interrupt handler function
+ * @dev: callback function of the data
+ * @time: time for timer
+ *
+ * This executes the "request_irq", returning NULL
+ * else "handle" on success.
+ */
+struct mpic_timer *mpic_request_timer(irq_handler_t fn, void *dev,
+					const struct timeval *time)
+{
+	struct mpic_timer *allocated_timer = NULL;
+
+	int ret = 0;
+
+	if (list_empty(&group_list))
+		return NULL;
+
+	if ((time->tv_sec + time->tv_usec) == 0 ||
+			time->tv_sec < 0 || time->tv_usec < 0)
+		return NULL;
+
+	if (time->tv_usec > ONE_SECOND)
+		return NULL;
+
+	allocated_timer = get_timer(time);
+	if (!allocated_timer)
+		return NULL;
+
+	ret = request_irq(allocated_timer->irq, fn, IRQF_TRIGGER_LOW,
+			"global-timer", dev);
+	if (ret)
+		return NULL;
+
+	allocated_timer->dev = dev;
+
+	return allocated_timer;
+}
+EXPORT_SYMBOL_GPL(mpic_request_timer);
+
+/**
+ * mpic_start_timer - start hardware timer
+ * @handle: the timer to be started.
+ *
+ * It will do ->fn(->dev) callback from the hardware interrupt at
+ * the ->timeval point in the future.
+ */
+void mpic_start_timer(struct mpic_timer *handle)
+{
+	struct group_priv *priv = container_of(handle, struct group_priv,
+			timer[handle->num]);
+
+	clrbits32(&priv->regs[handle->num].gtbcr, TIMER_STOP);
+}
+EXPORT_SYMBOL_GPL(mpic_start_timer);
+
+/**
+ * mpic_stop_timer - stop hardware timer
+ * @handle: the timer to be stoped
+ *
+ * The timer periodically generates an interrupt. Unless user stops the timer.
+ */
+void mpic_stop_timer(struct mpic_timer *handle)
+{
+	struct group_priv *priv = container_of(handle, struct group_priv,
+			timer[handle->num]);
+
+	setbits32(&priv->regs[handle->num].gtbcr, TIMER_STOP);
+}
+EXPORT_SYMBOL_GPL(mpic_stop_timer);
+
+/**
+ * mpic_free_timer - free hardware timer
+ * @handle: the timer to be removed.
+ *
+ * Free the timer.
+ *
+ * Note: can not be used in interrupt context.
+ */
+void mpic_free_timer(struct mpic_timer *handle)
+{
+	struct group_priv *priv = container_of(handle, struct group_priv,
+			timer[handle->num]);
+
+	struct cascade_priv *casc_priv = NULL;
+	unsigned long flags;
+
+	mpic_stop_timer(handle);
+
+	casc_priv = priv->timer[handle->num].cascade_handle;
+
+	free_irq(priv->timer[handle->num].irq, priv->timer[handle->num].dev);
+
+	spin_lock_irqsave(&priv->lock, flags);
+	if (casc_priv) {
+		u32 tmp;
+		tmp = casc_priv->tcr_value | (casc_priv->tcr_value <<
+					MPIC_TIMER_TCR_ROVR_OFFSET);
+		clrbits32(priv->group_tcr, tmp);
+		priv->idle |= casc_priv->cascade_map;
+		priv->timer[handle->num].cascade_handle = NULL;
+	} else {
+		priv->idle |= TIMER_OFFSET(handle->num);
+	}
+	spin_unlock_irqrestore(&priv->lock, flags);
+}
+EXPORT_SYMBOL_GPL(mpic_free_timer);
+
+static int group_get_freq(struct group_priv *priv)
+{
+	if (priv->flags & FSL_GLOBAL_TIMER) {
+		ccbfreq = fsl_get_sys_freq();
+		priv->timerfreq = ccbfreq;
+	} else {
+		priv->timerfreq = in_be32(priv->group_tfrr);
+	}
+
+	if (priv->timerfreq <= 0)
+		return -EINVAL;
+
+	return 0;
+}
+
+static int group_init_regmap(struct device_node *np, struct group_priv *priv)
+{
+	priv->group_tfrr = of_iomap(np, 0);
+	if (!priv->group_tfrr) {
+		pr_err("%s: cannot ioremap tfrr address.\n",
+				np->full_name);
+		return -EINVAL;
+	}
+
+	priv->regs = of_iomap(np, 1);
+	if (!priv->regs) {
+		pr_err("%s: cannot ioremap timer register address.\n",
+				np->full_name);
+		return -EINVAL;
+	}
+
+	if (!(priv->flags & FSL_GLOBAL_TIMER))
+		return 0;
+
+	priv->group_tcr = of_iomap(np, 2);
+	if (!priv->group_tcr) {
+		pr_err("%s: cannot ioremap tcr address.\n", np->full_name);
+		return -EINVAL;
+	}
+
+	return 0;
+}
+
+static int group_get_irq(struct device_node *np, struct group_priv *priv)
+{
+	const u32 all_timer[] = { 0, ALL_TIMER };
+	const u32 *p = NULL;
+	u32 offset;
+	u32 count;
+
+	unsigned int i = 0;
+	unsigned int j = 0;
+	unsigned int irq_index = 0;
+	int irq = 0;
+	int len = 0;
+
+	p = of_get_property(np, "available-ranges", &len);
+	if (p && len % (2 * sizeof(u32)) != 0) {
+		pr_err("%s: malformed fsl,available-ranges property.\n",
+				np->full_name);
+		return -EINVAL;
+	}
+
+	if (!p) {
+		p = all_timer;
+		len = sizeof(all_timer);
+	}
+
+	len /= 2 * sizeof(u32);
+
+	for (i = 0; i < len; i++) {
+		offset = p[i * 2];
+		count = p[i * 2 + 1];
+		for (j = 0; j < count; j++) {
+			irq = irq_of_parse_and_map(np, irq_index);
+			if (!irq)
+				break;
+			/* Set timer idle */
+			priv->idle |= TIMER_OFFSET((offset + j));
+			priv->timer[offset + j].irq = irq;
+			priv->timer[offset + j].num = offset + j;
+			irq_index++;
+		}
+	}
+
+	return 0;
+}
+
+static void group_init(struct device_node *np)
+{
+	struct group_priv *priv = NULL;
+	int ret = 0;
+
+	priv = kzalloc(sizeof(struct group_priv), GFP_KERNEL);
+	if (!priv) {
+		pr_err("%s: cannot allocate memory for group.\n",
+				np->full_name);
+		return;
+	}
+
+	if (of_device_is_compatible(np, "fsl,global-timer"))
+		priv->flags |= FSL_GLOBAL_TIMER;
+
+	ret = group_init_regmap(np, priv);
+	if (ret < 0)
+		goto out;
+
+	ret = group_get_freq(priv);
+	if (ret < 0)
+		goto out;
+
+	ret = group_get_irq(np, priv);
+	if (ret < 0)
+		goto out;
+
+	spin_lock_init(&priv->lock);
+
+	/* Init FSL timer hardware */
+	if (priv->flags & FSL_GLOBAL_TIMER)
+		setbits32(priv->group_tcr, MPIC_TIMER_TCR_CLKDIV_64);
+
+	list_add_tail(&priv->node, &group_list);
+
+	return;
+out:
+	if (priv->group_tcr)
+		iounmap(priv->group_tcr);
+
+	if (priv->regs)
+		iounmap(priv->regs);
+
+	if (priv->group_tfrr)
+		iounmap(priv->group_tfrr);
+
+	kfree(priv);
+}
+
+static const struct of_device_id mpic_timer_ids[] = {
+	{ .compatible = "open-pic,global-timer", },
+	{ .compatible = "fsl,global-timer", },
+	{},
+};
+
+static int __init mpic_timer_init(void)
+{
+	struct device_node *np = NULL;
+
+	for_each_node_by_type(np, "open-pic")
+		if (of_match_node(mpic_timer_ids, np))
+			group_init(np);
+
+	if (list_empty(&group_list))
+		return -ENODEV;
+
+	return 0;
+}
+arch_initcall(mpic_timer_init);
-- 
1.7.5.1

Re: [PATCH v2 2/2] powerpc/mpic: add global timer support

[Scott Wood]

On 08/10/2012 12:54 AM, Dongsheng.wang@freescale.com wrote:
> +static const struct of_device_id mpic_timer_ids[] = {
> +	{ .compatible = "open-pic,global-timer", },
> +	{ .compatible = "fsl,global-timer", },
> +	{},
> +};
> +
> +static int __init mpic_timer_init(void)
> +{
> +	struct device_node *np = NULL;
> +
> +	for_each_node_by_type(np, "open-pic")
> +		if (of_match_node(mpic_timer_ids, np))
> +			group_init(np);
> +
> +	if (list_empty(&group_list))
> +		return -ENODEV;
> +
> +	return 0;
> +}
> +arch_initcall(mpic_timer_init);
> 

Where do you distinguish an FSL timer from an openpic timer?  I thought
openpic timers didn't support cascading.

Oh, and don't probe by device_type.

-Scott

Re: [PATCH v2 2/2] powerpc/mpic: add global timer support

[Gala Kumar-B11780]

On Aug 10, 2012, at 2:40 PM, Scott Wood wrote:

> On 08/10/2012 12:54 AM, Dongsheng.wang@freescale.com wrote:
>> +static const struct of_device_id mpic_timer_ids[] =3D {
>> +	{ .compatible =3D "open-pic,global-timer", },
>> +	{ .compatible =3D "fsl,global-timer", },
>> +	{},
>> +};
>> +
>> +static int __init mpic_timer_init(void)
>> +{
>> +	struct device_node *np =3D NULL;
>> +
>> +	for_each_node_by_type(np, "open-pic")
>> +		if (of_match_node(mpic_timer_ids, np))
>> +			group_init(np);
>> +
>> +	if (list_empty(&group_list))
>> +		return -ENODEV;
>> +
>> +	return 0;
>> +}
>> +arch_initcall(mpic_timer_init);
>>=20
>=20
> Where do you distinguish an FSL timer from an openpic timer?  I thought
> openpic timers didn't support cascading.

in group_init()

+	if (of_device_is_compatible(np, "fsl,global-timer"))
+		priv->flags |=3D FSL_GLOBAL_TIMER;
+

- k

Re: [PATCH v2 2/2] powerpc/mpic: add global timer support

[Scott Wood]

On 08/10/2012 12:54 AM, Dongsheng.wang@freescale.com wrote:
> +static int group_get_freq(struct group_priv *priv)
> +{
> +	if (priv->flags & FSL_GLOBAL_TIMER) {
> +		ccbfreq = fsl_get_sys_freq();
> +		priv->timerfreq = ccbfreq;
> +	} else {
> +		priv->timerfreq = in_be32(priv->group_tfrr);
> +	}

FSL MPICs have TFRR too.  I'm not sure that the lack of fsl,mpic is a
good indication that TFRR is being set (e.g. we have old device trees
for FSL chips with U-Boot that are labelled as ordinary openpics).

> +
> +	if (priv->timerfreq <= 0)
> +		return -EINVAL;
> +
> +	return 0;
> +}

timerfreq is unsigned.  It can never be < 0.

> +
> +static int group_init_regmap(struct device_node *np, struct group_priv *priv)
> +{
> +	priv->group_tfrr = of_iomap(np, 0);
> +	if (!priv->group_tfrr) {
> +		pr_err("%s: cannot ioremap tfrr address.\n",
> +				np->full_name);
> +		return -EINVAL;
> +	}
> +
> +	priv->regs = of_iomap(np, 1);
> +	if (!priv->regs) {
> +		pr_err("%s: cannot ioremap timer register address.\n",
> +				np->full_name);
> +		return -EINVAL;
> +	}
> +
> +	if (!(priv->flags & FSL_GLOBAL_TIMER))
> +		return 0;
> +
> +	priv->group_tcr = of_iomap(np, 2);
> +	if (!priv->group_tcr) {
> +		pr_err("%s: cannot ioremap tcr address.\n", np->full_name);
> +		return -EINVAL;
> +	}

This is not compatible with existing mpic timer nodes.

> +	p = of_get_property(np, "available-ranges", &len);
> +	if (p && len % (2 * sizeof(u32)) != 0) {
> +		pr_err("%s: malformed fsl,available-ranges property.\n",
> +				np->full_name);
> +		return -EINVAL;
> +	}

You need to support fsl,available-ranges since that's in an accepted
binding and people could have partitioned setups already using it.

You also have a mismatch between the property you check and the error
string.

-Scott

Re: [PATCH v2 2/2] powerpc/mpic: add global timer support

[Tabi Timur-B04825]

On Fri, Aug 10, 2012 at 12:54 AM,  <Dongsheng.wang@freescale.com> wrote:
> From: Wang Dongsheng <Dongsheng.Wang@freescale.com>

> +EXPORT_SYMBOL_GPL(mpic_request_timer);

Make these EXPORT_SYMBOL.  No need for a GPL restriction.

--=20
Timur Tabi
Linux kernel developer at Freescale=

RE: [PATCH v2 2/2] powerpc/mpic: add global timer support

[Wang Dongsheng-B40534]

DQoNCj4gLS0tLS1PcmlnaW5hbCBNZXNzYWdlLS0tLS0NCj4gRnJvbTogV29vZCBTY290dC1CMDc0
MjENCj4gU2VudDogU2F0dXJkYXksIEF1Z3VzdCAxMSwgMjAxMiAzOjQwIEFNDQo+IFRvOiBXYW5n
IERvbmdzaGVuZy1CNDA1MzQNCj4gQ2M6IGJlbmhAa2VybmVsLmNyYXNoaW5nLm9yZzsgcGF1bHVz
QHNhbWJhLm9yZzsgbGludXhwcGMtDQo+IGRldkBsaXN0cy5vemxhYnMub3JnOyBHYWxhIEt1bWFy
LUIxMTc4MDsgTGkgWWFuZy1SNTg0NzINCj4gU3ViamVjdDogUmU6IFtQQVRDSCB2MiAyLzJdIHBv
d2VycGMvbXBpYzogYWRkIGdsb2JhbCB0aW1lciBzdXBwb3J0DQo+IA0KPiBPbiAwOC8xMC8yMDEy
IDEyOjU0IEFNLCBEb25nc2hlbmcud2FuZ0BmcmVlc2NhbGUuY29tIHdyb3RlOg0KPiA+ICtzdGF0
aWMgY29uc3Qgc3RydWN0IG9mX2RldmljZV9pZCBtcGljX3RpbWVyX2lkc1tdID0gew0KPiA+ICsJ
eyAuY29tcGF0aWJsZSA9ICJvcGVuLXBpYyxnbG9iYWwtdGltZXIiLCB9LA0KPiA+ICsJeyAuY29t
cGF0aWJsZSA9ICJmc2wsZ2xvYmFsLXRpbWVyIiwgfSwNCj4gPiArCXt9LA0KPiA+ICt9Ow0KPiA+
ICsNCj4gPiArc3RhdGljIGludCBfX2luaXQgbXBpY190aW1lcl9pbml0KHZvaWQpIHsNCj4gPiAr
CXN0cnVjdCBkZXZpY2Vfbm9kZSAqbnAgPSBOVUxMOw0KPiA+ICsNCj4gPiArCWZvcl9lYWNoX25v
ZGVfYnlfdHlwZShucCwgIm9wZW4tcGljIikNCj4gPiArCQlpZiAob2ZfbWF0Y2hfbm9kZShtcGlj
X3RpbWVyX2lkcywgbnApKQ0KPiA+ICsJCQlncm91cF9pbml0KG5wKTsNCj4gPiArDQo+ID4gKwlp
ZiAobGlzdF9lbXB0eSgmZ3JvdXBfbGlzdCkpDQo+ID4gKwkJcmV0dXJuIC1FTk9ERVY7DQo+ID4g
Kw0KPiA+ICsJcmV0dXJuIDA7DQo+ID4gK30NCj4gPiArYXJjaF9pbml0Y2FsbChtcGljX3RpbWVy
X2luaXQpOw0KPiANCj4gT2gsIGFuZCBkb24ndCBwcm9iZSBieSBkZXZpY2VfdHlwZS4NCj4gDQpb
V2FuZyBEb25nc2hlbmddIGZpbmUuIGZvcl9lYWNoX25vZGVfYnlfbmFtZS4NCg0KPiAtU2NvdHQN
Cg0K

RE: [PATCH v2 2/2] powerpc/mpic: add global timer support

[Li Yang-R58472]

DQoNCj4gLS0tLS1PcmlnaW5hbCBNZXNzYWdlLS0tLS0NCj4gRnJvbTogV2FuZyBEb25nc2hlbmct
QjQwNTM0DQo+IFNlbnQ6IE1vbmRheSwgQXVndXN0IDEzLCAyMDEyIDE6NTQgUE0NCj4gVG86IFdv
b2QgU2NvdHQtQjA3NDIxDQo+IENjOiBiZW5oQGtlcm5lbC5jcmFzaGluZy5vcmc7IHBhdWx1c0Bz
YW1iYS5vcmc7IGxpbnV4cHBjLQ0KPiBkZXZAbGlzdHMub3psYWJzLm9yZzsgR2FsYSBLdW1hci1C
MTE3ODA7IExpIFlhbmctUjU4NDcyDQo+IFN1YmplY3Q6IFJFOiBbUEFUQ0ggdjIgMi8yXSBwb3dl
cnBjL21waWM6IGFkZCBnbG9iYWwgdGltZXIgc3VwcG9ydA0KPiANCj4gDQo+IA0KPiA+IC0tLS0t
T3JpZ2luYWwgTWVzc2FnZS0tLS0tDQo+ID4gRnJvbTogV29vZCBTY290dC1CMDc0MjENCj4gPiBT
ZW50OiBTYXR1cmRheSwgQXVndXN0IDExLCAyMDEyIDM6NDAgQU0NCj4gPiBUbzogV2FuZyBEb25n
c2hlbmctQjQwNTM0DQo+ID4gQ2M6IGJlbmhAa2VybmVsLmNyYXNoaW5nLm9yZzsgcGF1bHVzQHNh
bWJhLm9yZzsgbGludXhwcGMtDQo+ID4gZGV2QGxpc3RzLm96bGFicy5vcmc7IEdhbGEgS3VtYXIt
QjExNzgwOyBMaSBZYW5nLVI1ODQ3Mg0KPiA+IFN1YmplY3Q6IFJlOiBbUEFUQ0ggdjIgMi8yXSBw
b3dlcnBjL21waWM6IGFkZCBnbG9iYWwgdGltZXIgc3VwcG9ydA0KPiA+DQo+ID4gT24gMDgvMTAv
MjAxMiAxMjo1NCBBTSwgRG9uZ3NoZW5nLndhbmdAZnJlZXNjYWxlLmNvbSB3cm90ZToNCj4gPiA+
ICtzdGF0aWMgY29uc3Qgc3RydWN0IG9mX2RldmljZV9pZCBtcGljX3RpbWVyX2lkc1tdID0gew0K
PiA+ID4gKwl7IC5jb21wYXRpYmxlID0gIm9wZW4tcGljLGdsb2JhbC10aW1lciIsIH0sDQo+ID4g
PiArCXsgLmNvbXBhdGlibGUgPSAiZnNsLGdsb2JhbC10aW1lciIsIH0sDQo+ID4gPiArCXt9LA0K
PiA+ID4gK307DQo+ID4gPiArDQo+ID4gPiArc3RhdGljIGludCBfX2luaXQgbXBpY190aW1lcl9p
bml0KHZvaWQpIHsNCj4gPiA+ICsJc3RydWN0IGRldmljZV9ub2RlICpucCA9IE5VTEw7DQo+ID4g
PiArDQo+ID4gPiArCWZvcl9lYWNoX25vZGVfYnlfdHlwZShucCwgIm9wZW4tcGljIikNCj4gPiA+
ICsJCWlmIChvZl9tYXRjaF9ub2RlKG1waWNfdGltZXJfaWRzLCBucCkpDQo+ID4gPiArCQkJZ3Jv
dXBfaW5pdChucCk7DQo+ID4gPiArDQo+ID4gPiArCWlmIChsaXN0X2VtcHR5KCZncm91cF9saXN0
KSkNCj4gPiA+ICsJCXJldHVybiAtRU5PREVWOw0KPiA+ID4gKw0KPiA+ID4gKwlyZXR1cm4gMDsN
Cj4gPiA+ICt9DQo+ID4gPiArYXJjaF9pbml0Y2FsbChtcGljX3RpbWVyX2luaXQpOw0KPiA+DQo+
ID4gT2gsIGFuZCBkb24ndCBwcm9iZSBieSBkZXZpY2VfdHlwZS4NCg0KQWN0dWFsbHkgaXQgZG9l
cyBtYXRjaCB0aGUgY29tcGF0aWJsZS4gIFRoZSBkZXZpY2VfdHlwZSBpcyBqdXN0IHRvIHNwZWVk
IHVwIHRoZSBzZWFyY2guICBJIGRvbid0IHRoaW5rIGl0J3MgYSBwcm9ibGVtIHVubGVzcyB0aGUg
ZGV2aWNlIHR5cGUgaXMgbm90IG1hbmRhdG9yeSBhbnkgbW9yZSBmb3IgZGVmaW5lZCB0eXBlcy4N
Cg0KLSBMZW8NCg==

RE: [PATCH v2 2/2] powerpc/mpic: add global timer support

[Wang Dongsheng-B40534]

DQoNCj4gLS0tLS1PcmlnaW5hbCBNZXNzYWdlLS0tLS0NCj4gRnJvbTogV29vZCBTY290dC1CMDc0
MjENCj4gU2VudDogU2F0dXJkYXksIEF1Z3VzdCAxMSwgMjAxMiA0OjM4IEFNDQo+IFRvOiBXYW5n
IERvbmdzaGVuZy1CNDA1MzQNCj4gQ2M6IGJlbmhAa2VybmVsLmNyYXNoaW5nLm9yZzsgcGF1bHVz
QHNhbWJhLm9yZzsgbGludXhwcGMtDQo+IGRldkBsaXN0cy5vemxhYnMub3JnOyBHYWxhIEt1bWFy
LUIxMTc4MDsgTGkgWWFuZy1SNTg0NzINCj4gU3ViamVjdDogUmU6IFtQQVRDSCB2MiAyLzJdIHBv
d2VycGMvbXBpYzogYWRkIGdsb2JhbCB0aW1lciBzdXBwb3J0DQo+IA0KPiBPbiAwOC8xMC8yMDEy
IDEyOjU0IEFNLCBEb25nc2hlbmcud2FuZ0BmcmVlc2NhbGUuY29tIHdyb3RlOg0KPiA+ICtzdGF0
aWMgaW50IGdyb3VwX2dldF9mcmVxKHN0cnVjdCBncm91cF9wcml2ICpwcml2KSB7DQo+ID4gKwlp
ZiAocHJpdi0+ZmxhZ3MgJiBGU0xfR0xPQkFMX1RJTUVSKSB7DQo+ID4gKwkJY2NiZnJlcSA9IGZz
bF9nZXRfc3lzX2ZyZXEoKTsNCj4gPiArCQlwcml2LT50aW1lcmZyZXEgPSBjY2JmcmVxOw0KPiA+
ICsJfSBlbHNlIHsNCj4gPiArCQlwcml2LT50aW1lcmZyZXEgPSBpbl9iZTMyKHByaXYtPmdyb3Vw
X3RmcnIpOw0KPiA+ICsJfQ0KPiANCj4gRlNMIE1QSUNzIGhhdmUgVEZSUiB0b28uICBJJ20gbm90
IHN1cmUgdGhhdCB0aGUgbGFjayBvZiBmc2wsbXBpYyBpcyBhDQo+IGdvb2QgaW5kaWNhdGlvbiB0
aGF0IFRGUlIgaXMgYmVpbmcgc2V0IChlLmcuIHdlIGhhdmUgb2xkIGRldmljZSB0cmVlcyBmb3IN
Cj4gRlNMIGNoaXBzIHdpdGggVS1Cb290IHRoYXQgYXJlIGxhYmVsbGVkIGFzIG9yZGluYXJ5IG9w
ZW5waWNzKS4NCj4gDQpbV2FuZyBEb25nc2hlbmddIHllcywgd2UgaGF2ZS4gQnV0IHdlIGRvIG5v
dCB1c2VkIGl0LiBUaGUgVEZSUiByZWdpc3RlciB2YWx1ZQ0KaXMgemVyby4gDQoNCj4gPiArDQo+
ID4gKwlpZiAocHJpdi0+dGltZXJmcmVxIDw9IDApDQo+ID4gKwkJcmV0dXJuIC1FSU5WQUw7DQo+
ID4gKw0KPiA+ICsJcmV0dXJuIDA7DQo+ID4gK30NCj4gDQo+IHRpbWVyZnJlcSBpcyB1bnNpZ25l
ZC4gIEl0IGNhbiBuZXZlciBiZSA8IDAuDQo+IA0KW1dhbmcgRG9uZ3NoZW5nXSBZZWFoLiBUaGFu
a3MuDQo+ID4gKw0KPiA+ICtzdGF0aWMgaW50IGdyb3VwX2luaXRfcmVnbWFwKHN0cnVjdCBkZXZp
Y2Vfbm9kZSAqbnAsIHN0cnVjdA0KPiA+ICtncm91cF9wcml2ICpwcml2KSB7DQo+ID4gKwlwcml2
LT5ncm91cF90ZnJyID0gb2ZfaW9tYXAobnAsIDApOw0KPiA+ICsJaWYgKCFwcml2LT5ncm91cF90
ZnJyKSB7DQo+ID4gKwkJcHJfZXJyKCIlczogY2Fubm90IGlvcmVtYXAgdGZyciBhZGRyZXNzLlxu
IiwNCj4gPiArCQkJCW5wLT5mdWxsX25hbWUpOw0KPiA+ICsJCXJldHVybiAtRUlOVkFMOw0KPiA+
ICsJfQ0KPiA+ICsNCj4gPiArCXByaXYtPnJlZ3MgPSBvZl9pb21hcChucCwgMSk7DQo+ID4gKwlp
ZiAoIXByaXYtPnJlZ3MpIHsNCj4gPiArCQlwcl9lcnIoIiVzOiBjYW5ub3QgaW9yZW1hcCB0aW1l
ciByZWdpc3RlciBhZGRyZXNzLlxuIiwNCj4gPiArCQkJCW5wLT5mdWxsX25hbWUpOw0KPiA+ICsJ
CXJldHVybiAtRUlOVkFMOw0KPiA+ICsJfQ0KPiA+ICsNCj4gPiArCWlmICghKHByaXYtPmZsYWdz
ICYgRlNMX0dMT0JBTF9USU1FUikpDQo+ID4gKwkJcmV0dXJuIDA7DQo+ID4gKw0KPiA+ICsJcHJp
di0+Z3JvdXBfdGNyID0gb2ZfaW9tYXAobnAsIDIpOw0KPiA+ICsJaWYgKCFwcml2LT5ncm91cF90
Y3IpIHsNCj4gPiArCQlwcl9lcnIoIiVzOiBjYW5ub3QgaW9yZW1hcCB0Y3IgYWRkcmVzcy5cbiIs
IG5wLT5mdWxsX25hbWUpOw0KPiA+ICsJCXJldHVybiAtRUlOVkFMOw0KPiA+ICsJfQ0KPiANCj4g
VGhpcyBpcyBub3QgY29tcGF0aWJsZSB3aXRoIGV4aXN0aW5nIG1waWMgdGltZXIgbm9kZXMuDQo+
IA0KW1dhbmcgRG9uZ3NoZW5nXSBZZWFoLCBuZXh0IHBhdGNoIHRvIHN1cHBvcnQgdGhhdC4NCg0K
PiA+ICsJcCA9IG9mX2dldF9wcm9wZXJ0eShucCwgImF2YWlsYWJsZS1yYW5nZXMiLCAmbGVuKTsN
Cj4gPiArCWlmIChwICYmIGxlbiAlICgyICogc2l6ZW9mKHUzMikpICE9IDApIHsNCj4gPiArCQlw
cl9lcnIoIiVzOiBtYWxmb3JtZWQgZnNsLGF2YWlsYWJsZS1yYW5nZXMgcHJvcGVydHkuXG4iLA0K
PiA+ICsJCQkJbnAtPmZ1bGxfbmFtZSk7DQo+ID4gKwkJcmV0dXJuIC1FSU5WQUw7DQo+ID4gKwl9
DQo+IA0KPiBZb3UgbmVlZCB0byBzdXBwb3J0IGZzbCxhdmFpbGFibGUtcmFuZ2VzIHNpbmNlIHRo
YXQncyBpbiBhbiBhY2NlcHRlZA0KPiBiaW5kaW5nIGFuZCBwZW9wbGUgY291bGQgaGF2ZSBwYXJ0
aXRpb25lZCBzZXR1cHMgYWxyZWFkeSB1c2luZyBpdC4NCj4gDQpbV2FuZyBEb25nc2hlbmddIEZT
TCBjaGlwIG9yIE9QRU4tUElDIHNwZWNpZmljYXRpb24oT25seSBhIGdyb3VwKQ0KaW4gZWFjaCBn
cm91cCBvbmx5IGZvdXIgdGltZXIuIFRoaXMgaXMgdW5pZmllZC4gU28gaSB1c2UgYSBnZW5lcmlj
IG5hbWUuDQpJIHRoaW5rIHRoZXJlIGlzIG5vdCBjb21wYXRpYmxlIHdpdGggZXhpc3RpbmcgbXBp
YyB0aW1lciBub2Rlcy4NCg0KCXAgPSBvZl9nZXRfcHJvcGVydHkobnAsICJhdmFpbGFibGUtcmFu
Z2VzIiwgJmxlbik7DQoJaWYgKCFwKQ0KCQlwID0gb2ZfZ2V0X3Byb3BlcnR5KG5wLCAiZnNsLGF2
YWlsYWJsZS1yYW5nZXMiLCAmbGVuKTsNCg0KCWlmIChwICYmIGxlbiAlICgyICogc2l6ZW9mKHUz
MikpICE9IDApIHsNCgkJcHJfZXJyKCIlczogbWFsZm9ybWVkIGZzbCxhdmFpbGFibGUtcmFuZ2Vz
IHByb3BlcnR5LlxuIiwNCgkJCQlucC0+ZnVsbF9uYW1lKTsNCgkJcmV0dXJuIC1FSU5WQUw7DQoJ
fQ0KDQo+IFlvdSBhbHNvIGhhdmUgYSBtaXNtYXRjaCBiZXR3ZWVuIHRoZSBwcm9wZXJ0eSB5b3Ug
Y2hlY2sgYW5kIHRoZSBlcnJvcg0KPiBzdHJpbmcuDQo+IA0KW1dhbmcgRG9uZ3NoZW5nXSBZZWFo
LiA6LSguDQoNCj4gLVNjb3R0DQoNCg==

RE: [PATCH v2 2/2] powerpc/mpic: add global timer support

[Wang Dongsheng-B40534]

> -----Original Message-----
> From: Tabi Timur-B04825
> Sent: Saturday, August 11, 2012 9:10 PM
> To: Wang Dongsheng-B40534
> Cc: benh@kernel.crashing.org; paulus@samba.org; Wood Scott-B07421; Gala
> Kumar-B11780; linuxppc-dev@lists.ozlabs.org
> Subject: Re: [PATCH v2 2/2] powerpc/mpic: add global timer support
>=20
> On Fri, Aug 10, 2012 at 12:54 AM,  <Dongsheng.wang@freescale.com> wrote:
> > From: Wang Dongsheng <Dongsheng.Wang@freescale.com>
>=20
> > +EXPORT_SYMBOL_GPL(mpic_request_timer);
>=20
> Make these EXPORT_SYMBOL.  No need for a GPL restriction.
>=20
[Wang Dongsheng] Why?
> --
> Timur Tabi
> Linux kernel developer at Freescale

RE: [PATCH v2 2/2] powerpc/mpic: add global timer support

[Wang Dongsheng-B40534]

> -----Original Message-----
> From: Linuxppc-dev [mailto:linuxppc-dev-
> bounces+b40534=3Dfreescale.com@lists.ozlabs.org] On Behalf Of Wang
> Dongsheng-B40534
> Sent: Monday, August 13, 2012 2:21 PM
> To: Tabi Timur-B04825
> Cc: Gala Kumar-B11780; paulus@samba.org; linuxppc-dev@lists.ozlabs.org;
> Wood Scott-B07421
> Subject: RE: [PATCH v2 2/2] powerpc/mpic: add global timer support
>=20
>=20
>=20
> > -----Original Message-----
> > From: Tabi Timur-B04825
> > Sent: Saturday, August 11, 2012 9:10 PM
> > To: Wang Dongsheng-B40534
> > Cc: benh@kernel.crashing.org; paulus@samba.org; Wood Scott-B07421;
> > Gala Kumar-B11780; linuxppc-dev@lists.ozlabs.org
> > Subject: Re: [PATCH v2 2/2] powerpc/mpic: add global timer support
> >
> > On Fri, Aug 10, 2012 at 12:54 AM,  <Dongsheng.wang@freescale.com> wrote=
:
> > > From: Wang Dongsheng <Dongsheng.Wang@freescale.com>
> >
> > > +EXPORT_SYMBOL_GPL(mpic_request_timer);
> >
> > Make these EXPORT_SYMBOL.  No need for a GPL restriction.
> >
> [Wang Dongsheng] Why?
[Wang Dongsheng] Sorry, I just see the mail. Thanks.

> > --
> > Timur Tabi
> > Linux kernel developer at Freescale
>=20
> _______________________________________________
> Linuxppc-dev mailing list
> Linuxppc-dev@lists.ozlabs.org
> https://lists.ozlabs.org/listinfo/linuxppc-dev

Re: [PATCH v2 2/2] powerpc/mpic: add global timer support

[Scott Wood]

On 08/13/2012 12:53 AM, Wang Dongsheng-B40534 wrote:
> 
> 
>> -----Original Message-----
>> From: Wood Scott-B07421
>> Sent: Saturday, August 11, 2012 3:40 AM
>> To: Wang Dongsheng-B40534
>> Cc: benh@kernel.crashing.org; paulus@samba.org; linuxppc-
>> dev@lists.ozlabs.org; Gala Kumar-B11780; Li Yang-R58472
>> Subject: Re: [PATCH v2 2/2] powerpc/mpic: add global timer support
>>
>> On 08/10/2012 12:54 AM, Dongsheng.wang@freescale.com wrote:
>>> +static const struct of_device_id mpic_timer_ids[] = {
>>> +	{ .compatible = "open-pic,global-timer", },
>>> +	{ .compatible = "fsl,global-timer", },
>>> +	{},
>>> +};
>>> +
>>> +static int __init mpic_timer_init(void) {
>>> +	struct device_node *np = NULL;
>>> +
>>> +	for_each_node_by_type(np, "open-pic")
>>> +		if (of_match_node(mpic_timer_ids, np))
>>> +			group_init(np);
>>> +
>>> +	if (list_empty(&group_list))
>>> +		return -ENODEV;
>>> +
>>> +	return 0;
>>> +}
>>> +arch_initcall(mpic_timer_init);
>>
>> Oh, and don't probe by device_type.
>>
> [Wang Dongsheng] fine. for_each_node_by_name.

No.  Probe by compatible only.

-Scott

Re: [PATCH v2 2/2] powerpc/mpic: add global timer support

[Scott Wood]

On 08/13/2012 01:17 AM, Li Yang-R58472 wrote:
> 
> 
>> -----Original Message-----
>> From: Wang Dongsheng-B40534
>> Sent: Monday, August 13, 2012 1:54 PM
>> To: Wood Scott-B07421
>> Cc: benh@kernel.crashing.org; paulus@samba.org; linuxppc-
>> dev@lists.ozlabs.org; Gala Kumar-B11780; Li Yang-R58472
>> Subject: RE: [PATCH v2 2/2] powerpc/mpic: add global timer support
>>
>>
>>
>>> -----Original Message-----
>>> From: Wood Scott-B07421
>>> Sent: Saturday, August 11, 2012 3:40 AM
>>> To: Wang Dongsheng-B40534
>>> Cc: benh@kernel.crashing.org; paulus@samba.org; linuxppc-
>>> dev@lists.ozlabs.org; Gala Kumar-B11780; Li Yang-R58472
>>> Subject: Re: [PATCH v2 2/2] powerpc/mpic: add global timer support
>>>
>>> On 08/10/2012 12:54 AM, Dongsheng.wang@freescale.com wrote:
>>>> +static const struct of_device_id mpic_timer_ids[] = {
>>>> +	{ .compatible = "open-pic,global-timer", },
>>>> +	{ .compatible = "fsl,global-timer", },
>>>> +	{},
>>>> +};
>>>> +
>>>> +static int __init mpic_timer_init(void) {
>>>> +	struct device_node *np = NULL;
>>>> +
>>>> +	for_each_node_by_type(np, "open-pic")
>>>> +		if (of_match_node(mpic_timer_ids, np))
>>>> +			group_init(np);
>>>> +
>>>> +	if (list_empty(&group_list))
>>>> +		return -ENODEV;
>>>> +
>>>> +	return 0;
>>>> +}
>>>> +arch_initcall(mpic_timer_init);
>>>
>>> Oh, and don't probe by device_type.
> 
> Actually it does match the compatible.  The device_type is just to
> speed up the search.  I don't think it's a problem unless the device
> type is not mandatory any more for defined types.

Doesn't matter (and I doubt it provides any significant speed up
compared to a search by compatible, and in any case this is not
performance critical).  device_type is deprecated outside certain
specific legacy uses.  Get rid of it.

-Scott

Re: [PATCH v2 2/2] powerpc/mpic: add global timer support

[Scott Wood]

On 08/13/2012 01:18 AM, Wang Dongsheng-B40534 wrote:
>>> +	p = of_get_property(np, "available-ranges", &len);
>>> +	if (p && len % (2 * sizeof(u32)) != 0) {
>>> +		pr_err("%s: malformed fsl,available-ranges property.\n",
>>> +				np->full_name);
>>> +		return -EINVAL;
>>> +	}
>>
>> You need to support fsl,available-ranges since that's in an accepted
>> binding and people could have partitioned setups already using it.
>>
> [Wang Dongsheng] FSL chip or OPEN-PIC specification(Only a group)
> in each group only four timer. This is unified. So i use a generic name.
> I think there is not compatible with existing mpic timer nodes.

We need to be compatible with existing trees, so you'd need to check for
both -- but I think any further discussion of the details is premature
until we decide whether this is worthwhile to begin with (both the
support of non-FSL timers, and the creation of a new device tree binding
which will not be implemented by many of the machines that have non-FSL
openpic because they run real Open Firmware).

-Scott

RE: [PATCH v2 2/2] powerpc/mpic: add global timer support

[Wang Dongsheng-B40534]

DQoNCj4gLS0tLS1PcmlnaW5hbCBNZXNzYWdlLS0tLS0NCj4gRnJvbTogV29vZCBTY290dC1CMDc0
MjENCj4gU2VudDogVHVlc2RheSwgQXVndXN0IDE0LCAyMDEyIDE6MzcgQU0NCj4gVG86IFdhbmcg
RG9uZ3NoZW5nLUI0MDUzNA0KPiBDYzogV29vZCBTY290dC1CMDc0MjE7IGJlbmhAa2VybmVsLmNy
YXNoaW5nLm9yZzsgcGF1bHVzQHNhbWJhLm9yZzsNCj4gbGludXhwcGMtZGV2QGxpc3RzLm96bGFi
cy5vcmc7IEdhbGEgS3VtYXItQjExNzgwOyBMaSBZYW5nLVI1ODQ3Mg0KPiBTdWJqZWN0OiBSZTog
W1BBVENIIHYyIDIvMl0gcG93ZXJwYy9tcGljOiBhZGQgZ2xvYmFsIHRpbWVyIHN1cHBvcnQNCj4g
DQo+IE9uIDA4LzEzLzIwMTIgMDE6MTggQU0sIFdhbmcgRG9uZ3NoZW5nLUI0MDUzNCB3cm90ZToN
Cj4gPj4+ICsJcCA9IG9mX2dldF9wcm9wZXJ0eShucCwgImF2YWlsYWJsZS1yYW5nZXMiLCAmbGVu
KTsNCj4gPj4+ICsJaWYgKHAgJiYgbGVuICUgKDIgKiBzaXplb2YodTMyKSkgIT0gMCkgew0KPiA+
Pj4gKwkJcHJfZXJyKCIlczogbWFsZm9ybWVkIGZzbCxhdmFpbGFibGUtcmFuZ2VzIHByb3BlcnR5
LlxuIiwNCj4gPj4+ICsJCQkJbnAtPmZ1bGxfbmFtZSk7DQo+ID4+PiArCQlyZXR1cm4gLUVJTlZB
TDsNCj4gPj4+ICsJfQ0KPiA+Pg0KPiA+PiBZb3UgbmVlZCB0byBzdXBwb3J0IGZzbCxhdmFpbGFi
bGUtcmFuZ2VzIHNpbmNlIHRoYXQncyBpbiBhbiBhY2NlcHRlZA0KPiA+PiBiaW5kaW5nIGFuZCBw
ZW9wbGUgY291bGQgaGF2ZSBwYXJ0aXRpb25lZCBzZXR1cHMgYWxyZWFkeSB1c2luZyBpdC4NCj4g
Pj4NCj4gPiBbV2FuZyBEb25nc2hlbmddIEZTTCBjaGlwIG9yIE9QRU4tUElDIHNwZWNpZmljYXRp
b24oT25seSBhIGdyb3VwKSBpbg0KPiA+IGVhY2ggZ3JvdXAgb25seSBmb3VyIHRpbWVyLiBUaGlz
IGlzIHVuaWZpZWQuIFNvIGkgdXNlIGEgZ2VuZXJpYyBuYW1lLg0KPiA+IEkgdGhpbmsgdGhlcmUg
aXMgbm90IGNvbXBhdGlibGUgd2l0aCBleGlzdGluZyBtcGljIHRpbWVyIG5vZGVzLg0KPiANCj4g
V2UgbmVlZCB0byBiZSBjb21wYXRpYmxlIHdpdGggZXhpc3RpbmcgdHJlZXMsIHNvIHlvdSdkIG5l
ZWQgdG8gY2hlY2sgZm9yDQo+IGJvdGggLS0gYnV0IEkgdGhpbmsgYW55IGZ1cnRoZXIgZGlzY3Vz
c2lvbiBvZiB0aGUgZGV0YWlscyBpcyBwcmVtYXR1cmUNCj4gdW50aWwgd2UgZGVjaWRlIHdoZXRo
ZXIgdGhpcyBpcyB3b3J0aHdoaWxlIHRvIGJlZ2luIHdpdGggKGJvdGggdGhlDQo+IHN1cHBvcnQg
b2Ygbm9uLUZTTCB0aW1lcnMsIGFuZCB0aGUgY3JlYXRpb24gb2YgYSBuZXcgZGV2aWNlIHRyZWUg
YmluZGluZw0KPiB3aGljaCB3aWxsIG5vdCBiZSBpbXBsZW1lbnRlZCBieSBtYW55IG9mIHRoZSBt
YWNoaW5lcyB0aGF0IGhhdmUgbm9uLUZTTA0KPiBvcGVucGljIGJlY2F1c2UgdGhleSBydW4gcmVh
bCBPcGVuIEZpcm13YXJlKS4NCj4gDQpbV2FuZyBEb25nc2hlbmddIA0KCXAgPSBvZl9nZXRfcHJv
cGVydHkobnAsICJhdmFpbGFibGUtcmFuZ2VzIiwgJmxlbik7DQoJaWYgKCFwKQ0KCQlwID0gb2Zf
Z2V0X3Byb3BlcnR5KG5wLCAiZnNsLGF2YWlsYWJsZS1yYW5nZXMiLCAmbGVuKTsNCgkNCgl0aGlz
IGNvZGUgYmUgY29tcGF0aWJsZSB3aXRoIGV4aXN0aW5nIHRyZWVzLg0KCQ0KPiAtU2NvdHQNCg0K

Re: [PATCH v2 2/2] powerpc/mpic: add global timer support

[Scott Wood]

On 08/13/2012 09:00 PM, Wang Dongsheng-B40534 wrote:
> 
> 
>> -----Original Message-----
>> From: Wood Scott-B07421
>> Sent: Tuesday, August 14, 2012 1:37 AM
>> To: Wang Dongsheng-B40534
>> Cc: Wood Scott-B07421; benh@kernel.crashing.org; paulus@samba.org;
>> linuxppc-dev@lists.ozlabs.org; Gala Kumar-B11780; Li Yang-R58472
>> Subject: Re: [PATCH v2 2/2] powerpc/mpic: add global timer support
>>
>> On 08/13/2012 01:18 AM, Wang Dongsheng-B40534 wrote:
>>>>> +	p = of_get_property(np, "available-ranges", &len);
>>>>> +	if (p && len % (2 * sizeof(u32)) != 0) {
>>>>> +		pr_err("%s: malformed fsl,available-ranges property.\n",
>>>>> +				np->full_name);
>>>>> +		return -EINVAL;
>>>>> +	}
>>>>
>>>> You need to support fsl,available-ranges since that's in an accepted
>>>> binding and people could have partitioned setups already using it.
>>>>
>>> [Wang Dongsheng] FSL chip or OPEN-PIC specification(Only a group) in
>>> each group only four timer. This is unified. So i use a generic name.
>>> I think there is not compatible with existing mpic timer nodes.
>>
>> We need to be compatible with existing trees, so you'd need to check for
>> both -- but I think any further discussion of the details is premature
>> until we decide whether this is worthwhile to begin with (both the
>> support of non-FSL timers, and the creation of a new device tree binding
>> which will not be implemented by many of the machines that have non-FSL
>> openpic because they run real Open Firmware).
>>
> [Wang Dongsheng] 
> 	p = of_get_property(np, "available-ranges", &len);
> 	if (!p)
> 		p = of_get_property(np, "fsl,available-ranges", &len);
> 	
> 	this code be compatible with existing trees.

Yes, that's what I meant by checking both.

I still think we need to discuss why we're doing this first.  What
specific machines are going to have these new openpic timer nodes?

-Scott

RE: [PATCH v2 2/2] powerpc/mpic: add global timer support

[Wang Dongsheng-B40534]

DQoNCj4gLS0tLS1PcmlnaW5hbCBNZXNzYWdlLS0tLS0NCj4gRnJvbTogV29vZCBTY290dC1CMDc0
MjENCj4gU2VudDogVHVlc2RheSwgQXVndXN0IDE0LCAyMDEyIDEyOjQ5IEFNDQo+IFRvOiBXYW5n
IERvbmdzaGVuZy1CNDA1MzQNCj4gQ2M6IFdvb2QgU2NvdHQtQjA3NDIxOyBiZW5oQGtlcm5lbC5j
cmFzaGluZy5vcmc7IHBhdWx1c0BzYW1iYS5vcmc7DQo+IGxpbnV4cHBjLWRldkBsaXN0cy5vemxh
YnMub3JnOyBHYWxhIEt1bWFyLUIxMTc4MDsgTGkgWWFuZy1SNTg0NzINCj4gU3ViamVjdDogUmU6
IFtQQVRDSCB2MiAyLzJdIHBvd2VycGMvbXBpYzogYWRkIGdsb2JhbCB0aW1lciBzdXBwb3J0DQo+
IA0KPiBPbiAwOC8xMy8yMDEyIDEyOjUzIEFNLCBXYW5nIERvbmdzaGVuZy1CNDA1MzQgd3JvdGU6
DQo+ID4NCj4gPg0KPiA+PiAtLS0tLU9yaWdpbmFsIE1lc3NhZ2UtLS0tLQ0KPiA+PiBGcm9tOiBX
b29kIFNjb3R0LUIwNzQyMQ0KPiA+PiBTZW50OiBTYXR1cmRheSwgQXVndXN0IDExLCAyMDEyIDM6
NDAgQU0NCj4gPj4gVG86IFdhbmcgRG9uZ3NoZW5nLUI0MDUzNA0KPiA+PiBDYzogYmVuaEBrZXJu
ZWwuY3Jhc2hpbmcub3JnOyBwYXVsdXNAc2FtYmEub3JnOyBsaW51eHBwYy0NCj4gPj4gZGV2QGxp
c3RzLm96bGFicy5vcmc7IEdhbGEgS3VtYXItQjExNzgwOyBMaSBZYW5nLVI1ODQ3Mg0KPiA+PiBT
dWJqZWN0OiBSZTogW1BBVENIIHYyIDIvMl0gcG93ZXJwYy9tcGljOiBhZGQgZ2xvYmFsIHRpbWVy
IHN1cHBvcnQNCj4gPj4NCj4gPj4gT24gMDgvMTAvMjAxMiAxMjo1NCBBTSwgRG9uZ3NoZW5nLndh
bmdAZnJlZXNjYWxlLmNvbSB3cm90ZToNCj4gPj4+ICtzdGF0aWMgY29uc3Qgc3RydWN0IG9mX2Rl
dmljZV9pZCBtcGljX3RpbWVyX2lkc1tdID0gew0KPiA+Pj4gKwl7IC5jb21wYXRpYmxlID0gIm9w
ZW4tcGljLGdsb2JhbC10aW1lciIsIH0sDQo+ID4+PiArCXsgLmNvbXBhdGlibGUgPSAiZnNsLGds
b2JhbC10aW1lciIsIH0sDQo+ID4+PiArCXt9LA0KPiA+Pj4gK307DQo+ID4+PiArDQo+ID4+PiAr
c3RhdGljIGludCBfX2luaXQgbXBpY190aW1lcl9pbml0KHZvaWQpIHsNCj4gPj4+ICsJc3RydWN0
IGRldmljZV9ub2RlICpucCA9IE5VTEw7DQo+ID4+PiArDQo+ID4+PiArCWZvcl9lYWNoX25vZGVf
YnlfdHlwZShucCwgIm9wZW4tcGljIikNCj4gPj4+ICsJCWlmIChvZl9tYXRjaF9ub2RlKG1waWNf
dGltZXJfaWRzLCBucCkpDQo+ID4+PiArCQkJZ3JvdXBfaW5pdChucCk7DQo+ID4+PiArDQo+ID4+
PiArCWlmIChsaXN0X2VtcHR5KCZncm91cF9saXN0KSkNCj4gPj4+ICsJCXJldHVybiAtRU5PREVW
Ow0KPiA+Pj4gKw0KPiA+Pj4gKwlyZXR1cm4gMDsNCj4gPj4+ICt9DQo+ID4+PiArYXJjaF9pbml0
Y2FsbChtcGljX3RpbWVyX2luaXQpOw0KPiA+Pg0KPiA+PiBPaCwgYW5kIGRvbid0IHByb2JlIGJ5
IGRldmljZV90eXBlLg0KPiA+Pg0KPiA+IFtXYW5nIERvbmdzaGVuZ10gZmluZS4gZm9yX2VhY2hf
bm9kZV9ieV9uYW1lLg0KPiANCj4gTm8uICBQcm9iZSBieSBjb21wYXRpYmxlIG9ubHkuDQo+IA0K
W1dhbmcgRG9uZ3NoZW5nXSBJIGxvb2tlZCBkZXZpY2V0cmVlJ3MgQVBJLiANCg0KCWZvcl9lYWNo
X21hdGNoaW5nX25vZGUobnAsIG1waWNfdGltZXJfaWRzKSBsb29rcyBiZXR0ZXIuIFRoYW5rcy4N
CiAgICAgICAgICAgICAgICAgICAgICAgIA0KDQo+IC1TY290dA0KDQo=

RE: [PATCH v2 2/2] powerpc/mpic: add global timer support

[Wang Dongsheng-B40534]

DQoNCj4gLS0tLS1PcmlnaW5hbCBNZXNzYWdlLS0tLS0NCj4gRnJvbTogV29vZCBTY290dC1CMDc0
MjENCj4gU2VudDogVHVlc2RheSwgQXVndXN0IDE0LCAyMDEyIDEwOjA1IEFNDQo+IFRvOiBXYW5n
IERvbmdzaGVuZy1CNDA1MzQNCj4gQ2M6IFdvb2QgU2NvdHQtQjA3NDIxOyBiZW5oQGtlcm5lbC5j
cmFzaGluZy5vcmc7IHBhdWx1c0BzYW1iYS5vcmc7DQo+IGxpbnV4cHBjLWRldkBsaXN0cy5vemxh
YnMub3JnOyBHYWxhIEt1bWFyLUIxMTc4MDsgTGkgWWFuZy1SNTg0NzINCj4gU3ViamVjdDogUmU6
IFtQQVRDSCB2MiAyLzJdIHBvd2VycGMvbXBpYzogYWRkIGdsb2JhbCB0aW1lciBzdXBwb3J0DQo+
IA0KPiBPbiAwOC8xMy8yMDEyIDA5OjAwIFBNLCBXYW5nIERvbmdzaGVuZy1CNDA1MzQgd3JvdGU6
DQo+ID4NCj4gPg0KPiA+PiAtLS0tLU9yaWdpbmFsIE1lc3NhZ2UtLS0tLQ0KPiA+PiBGcm9tOiBX
b29kIFNjb3R0LUIwNzQyMQ0KPiA+PiBTZW50OiBUdWVzZGF5LCBBdWd1c3QgMTQsIDIwMTIgMToz
NyBBTQ0KPiA+PiBUbzogV2FuZyBEb25nc2hlbmctQjQwNTM0DQo+ID4+IENjOiBXb29kIFNjb3R0
LUIwNzQyMTsgYmVuaEBrZXJuZWwuY3Jhc2hpbmcub3JnOyBwYXVsdXNAc2FtYmEub3JnOw0KPiA+
PiBsaW51eHBwYy1kZXZAbGlzdHMub3psYWJzLm9yZzsgR2FsYSBLdW1hci1CMTE3ODA7IExpIFlh
bmctUjU4NDcyDQo+ID4+IFN1YmplY3Q6IFJlOiBbUEFUQ0ggdjIgMi8yXSBwb3dlcnBjL21waWM6
IGFkZCBnbG9iYWwgdGltZXIgc3VwcG9ydA0KPiA+Pg0KPiA+PiBPbiAwOC8xMy8yMDEyIDAxOjE4
IEFNLCBXYW5nIERvbmdzaGVuZy1CNDA1MzQgd3JvdGU6DQo+ID4+Pj4+ICsJcCA9IG9mX2dldF9w
cm9wZXJ0eShucCwgImF2YWlsYWJsZS1yYW5nZXMiLCAmbGVuKTsNCj4gPj4+Pj4gKwlpZiAocCAm
JiBsZW4gJSAoMiAqIHNpemVvZih1MzIpKSAhPSAwKSB7DQo+ID4+Pj4+ICsJCXByX2VycigiJXM6
IG1hbGZvcm1lZCBmc2wsYXZhaWxhYmxlLXJhbmdlcyBwcm9wZXJ0eS5cbiIsDQo+ID4+Pj4+ICsJ
CQkJbnAtPmZ1bGxfbmFtZSk7DQo+ID4+Pj4+ICsJCXJldHVybiAtRUlOVkFMOw0KPiA+Pj4+PiAr
CX0NCj4gPj4+Pg0KPiA+Pj4+IFlvdSBuZWVkIHRvIHN1cHBvcnQgZnNsLGF2YWlsYWJsZS1yYW5n
ZXMgc2luY2UgdGhhdCdzIGluIGFuDQo+ID4+Pj4gYWNjZXB0ZWQgYmluZGluZyBhbmQgcGVvcGxl
IGNvdWxkIGhhdmUgcGFydGl0aW9uZWQgc2V0dXBzIGFscmVhZHkNCj4gdXNpbmcgaXQuDQo+ID4+
Pj4NCj4gPj4+IFtXYW5nIERvbmdzaGVuZ10gRlNMIGNoaXAgb3IgT1BFTi1QSUMgc3BlY2lmaWNh
dGlvbihPbmx5IGEgZ3JvdXApIGluDQo+ID4+PiBlYWNoIGdyb3VwIG9ubHkgZm91ciB0aW1lci4g
VGhpcyBpcyB1bmlmaWVkLiBTbyBpIHVzZSBhIGdlbmVyaWMgbmFtZS4NCj4gPj4+IEkgdGhpbmsg
dGhlcmUgaXMgbm90IGNvbXBhdGlibGUgd2l0aCBleGlzdGluZyBtcGljIHRpbWVyIG5vZGVzLg0K
PiA+Pg0KPiA+PiBXZSBuZWVkIHRvIGJlIGNvbXBhdGlibGUgd2l0aCBleGlzdGluZyB0cmVlcywg
c28geW91J2QgbmVlZCB0byBjaGVjaw0KPiA+PiBmb3IgYm90aCAtLSBidXQgSSB0aGluayBhbnkg
ZnVydGhlciBkaXNjdXNzaW9uIG9mIHRoZSBkZXRhaWxzIGlzDQo+ID4+IHByZW1hdHVyZSB1bnRp
bCB3ZSBkZWNpZGUgd2hldGhlciB0aGlzIGlzIHdvcnRod2hpbGUgdG8gYmVnaW4gd2l0aA0KPiA+
PiAoYm90aCB0aGUgc3VwcG9ydCBvZiBub24tRlNMIHRpbWVycywgYW5kIHRoZSBjcmVhdGlvbiBv
ZiBhIG5ldyBkZXZpY2UNCj4gPj4gdHJlZSBiaW5kaW5nIHdoaWNoIHdpbGwgbm90IGJlIGltcGxl
bWVudGVkIGJ5IG1hbnkgb2YgdGhlIG1hY2hpbmVzDQo+ID4+IHRoYXQgaGF2ZSBub24tRlNMIG9w
ZW5waWMgYmVjYXVzZSB0aGV5IHJ1biByZWFsIE9wZW4gRmlybXdhcmUpLg0KPiA+Pg0KPiA+IFtX
YW5nIERvbmdzaGVuZ10NCj4gPiAJcCA9IG9mX2dldF9wcm9wZXJ0eShucCwgImF2YWlsYWJsZS1y
YW5nZXMiLCAmbGVuKTsNCj4gPiAJaWYgKCFwKQ0KPiA+IAkJcCA9IG9mX2dldF9wcm9wZXJ0eShu
cCwgImZzbCxhdmFpbGFibGUtcmFuZ2VzIiwgJmxlbik7DQo+ID4NCj4gPiAJdGhpcyBjb2RlIGJl
IGNvbXBhdGlibGUgd2l0aCBleGlzdGluZyB0cmVlcy4NCj4gDQo+IFllcywgdGhhdCdzIHdoYXQg
SSBtZWFudCBieSBjaGVja2luZyBib3RoLg0KPiANCj4gSSBzdGlsbCB0aGluayB3ZSBuZWVkIHRv
IGRpc2N1c3Mgd2h5IHdlJ3JlIGRvaW5nIHRoaXMgZmlyc3QuICBXaGF0DQo+IHNwZWNpZmljIG1h
Y2hpbmVzIGFyZSBnb2luZyB0byBoYXZlIHRoZXNlIG5ldyBvcGVucGljIHRpbWVyIG5vZGVzPw0K
PiANCltXYW5nIERvbmdzaGVuZ10gSXQncyBzdXBwb3J0IHRvIHBvd2VyIG1hbmFnZW1lbnQgYXdh
a2VuaW5nLiBBdCBwcmVzZW50LCANCnRoZSBwb3dlciBtYW5hZ2VtZW50IG1vcmUgYW5kIG1vcmUg
aW1wb3J0YW50LiBUaGlzIHdheSBpcyBpbXBvcnRhbnQgdG8gd2FrZQ0KdXAgbWFjaGluZS4gQXQg
bGVhc3QgbmVlZCBzdXBwb3J0IHBvd2VyIG1hbmFnZW1lbnQgb2YgbWFjaGluZSBzdGlsbCBuZWVk
cw0Kc3VjaCBhIGRyaXZlci4NCg0KPiAtU2NvdHQNCg0K

Re: [PATCH v2 2/2] powerpc/mpic: add global timer support

[Scott Wood]

On 08/13/2012 09:15 PM, Wang Dongsheng-B40534 wrote:
> 
> 
>> -----Original Message-----
>> From: Wood Scott-B07421
>> Sent: Tuesday, August 14, 2012 10:05 AM
>> To: Wang Dongsheng-B40534
>> Cc: Wood Scott-B07421; benh@kernel.crashing.org; paulus@samba.org;
>> linuxppc-dev@lists.ozlabs.org; Gala Kumar-B11780; Li Yang-R58472
>> Subject: Re: [PATCH v2 2/2] powerpc/mpic: add global timer support
>>
>> On 08/13/2012 09:00 PM, Wang Dongsheng-B40534 wrote:
>>>
>>>
>>>> -----Original Message-----
>>>> From: Wood Scott-B07421
>>>> Sent: Tuesday, August 14, 2012 1:37 AM
>>>> To: Wang Dongsheng-B40534
>>>> Cc: Wood Scott-B07421; benh@kernel.crashing.org; paulus@samba.org;
>>>> linuxppc-dev@lists.ozlabs.org; Gala Kumar-B11780; Li Yang-R58472
>>>> Subject: Re: [PATCH v2 2/2] powerpc/mpic: add global timer support
>>>>
>>>> On 08/13/2012 01:18 AM, Wang Dongsheng-B40534 wrote:
>>>>>>> +	p = of_get_property(np, "available-ranges", &len);
>>>>>>> +	if (p && len % (2 * sizeof(u32)) != 0) {
>>>>>>> +		pr_err("%s: malformed fsl,available-ranges property.\n",
>>>>>>> +				np->full_name);
>>>>>>> +		return -EINVAL;
>>>>>>> +	}
>>>>>>
>>>>>> You need to support fsl,available-ranges since that's in an
>>>>>> accepted binding and people could have partitioned setups already
>> using it.
>>>>>>
>>>>> [Wang Dongsheng] FSL chip or OPEN-PIC specification(Only a group) in
>>>>> each group only four timer. This is unified. So i use a generic name.
>>>>> I think there is not compatible with existing mpic timer nodes.
>>>>
>>>> We need to be compatible with existing trees, so you'd need to check
>>>> for both -- but I think any further discussion of the details is
>>>> premature until we decide whether this is worthwhile to begin with
>>>> (both the support of non-FSL timers, and the creation of a new device
>>>> tree binding which will not be implemented by many of the machines
>>>> that have non-FSL openpic because they run real Open Firmware).
>>>>
>>> [Wang Dongsheng]
>>> 	p = of_get_property(np, "available-ranges", &len);
>>> 	if (!p)
>>> 		p = of_get_property(np, "fsl,available-ranges", &len);
>>>
>>> 	this code be compatible with existing trees.
>>
>> Yes, that's what I meant by checking both.
>>
>> I still think we need to discuss why we're doing this first.  What
>> specific machines are going to have these new openpic timer nodes?
>>
> [Wang Dongsheng] It's support to power management awakening. At present, 
> the power management more and more important. This way is important to wake
> up machine. At least need support power management of machine still needs
> such a driver.

I mean specifically for the non-Freescale openpic nodes.

-Scott

RE: [PATCH v2 2/2] powerpc/mpic: add global timer support

[Wang Dongsheng-B40534]

DQoNCj4gLS0tLS1PcmlnaW5hbCBNZXNzYWdlLS0tLS0NCj4gRnJvbTogV29vZCBTY290dC1CMDc0
MjENCj4gU2VudDogVHVlc2RheSwgQXVndXN0IDE0LCAyMDEyIDEwOjE5IEFNDQo+IFRvOiBXYW5n
IERvbmdzaGVuZy1CNDA1MzQNCj4gQ2M6IFdvb2QgU2NvdHQtQjA3NDIxOyBiZW5oQGtlcm5lbC5j
cmFzaGluZy5vcmc7IHBhdWx1c0BzYW1iYS5vcmc7DQo+IGxpbnV4cHBjLWRldkBsaXN0cy5vemxh
YnMub3JnOyBHYWxhIEt1bWFyLUIxMTc4MDsgTGkgWWFuZy1SNTg0NzINCj4gU3ViamVjdDogUmU6
IFtQQVRDSCB2MiAyLzJdIHBvd2VycGMvbXBpYzogYWRkIGdsb2JhbCB0aW1lciBzdXBwb3J0DQo+
IA0KPiBPbiAwOC8xMy8yMDEyIDA5OjE1IFBNLCBXYW5nIERvbmdzaGVuZy1CNDA1MzQgd3JvdGU6
DQo+ID4NCj4gPg0KPiA+PiAtLS0tLU9yaWdpbmFsIE1lc3NhZ2UtLS0tLQ0KPiA+PiBGcm9tOiBX
b29kIFNjb3R0LUIwNzQyMQ0KPiA+PiBTZW50OiBUdWVzZGF5LCBBdWd1c3QgMTQsIDIwMTIgMTA6
MDUgQU0NCj4gPj4gVG86IFdhbmcgRG9uZ3NoZW5nLUI0MDUzNA0KPiA+PiBDYzogV29vZCBTY290
dC1CMDc0MjE7IGJlbmhAa2VybmVsLmNyYXNoaW5nLm9yZzsgcGF1bHVzQHNhbWJhLm9yZzsNCj4g
Pj4gbGludXhwcGMtZGV2QGxpc3RzLm96bGFicy5vcmc7IEdhbGEgS3VtYXItQjExNzgwOyBMaSBZ
YW5nLVI1ODQ3Mg0KPiA+PiBTdWJqZWN0OiBSZTogW1BBVENIIHYyIDIvMl0gcG93ZXJwYy9tcGlj
OiBhZGQgZ2xvYmFsIHRpbWVyIHN1cHBvcnQNCj4gPj4NCj4gPj4gT24gMDgvMTMvMjAxMiAwOTow
MCBQTSwgV2FuZyBEb25nc2hlbmctQjQwNTM0IHdyb3RlOg0KPiA+Pj4NCj4gPj4+DQo+ID4+Pj4g
LS0tLS1PcmlnaW5hbCBNZXNzYWdlLS0tLS0NCj4gPj4+PiBGcm9tOiBXb29kIFNjb3R0LUIwNzQy
MQ0KPiA+Pj4+IFNlbnQ6IFR1ZXNkYXksIEF1Z3VzdCAxNCwgMjAxMiAxOjM3IEFNDQo+ID4+Pj4g
VG86IFdhbmcgRG9uZ3NoZW5nLUI0MDUzNA0KPiA+Pj4+IENjOiBXb29kIFNjb3R0LUIwNzQyMTsg
YmVuaEBrZXJuZWwuY3Jhc2hpbmcub3JnOyBwYXVsdXNAc2FtYmEub3JnOw0KPiA+Pj4+IGxpbnV4
cHBjLWRldkBsaXN0cy5vemxhYnMub3JnOyBHYWxhIEt1bWFyLUIxMTc4MDsgTGkgWWFuZy1SNTg0
NzINCj4gPj4+PiBTdWJqZWN0OiBSZTogW1BBVENIIHYyIDIvMl0gcG93ZXJwYy9tcGljOiBhZGQg
Z2xvYmFsIHRpbWVyIHN1cHBvcnQNCj4gPj4+Pg0KPiA+Pj4+IE9uIDA4LzEzLzIwMTIgMDE6MTgg
QU0sIFdhbmcgRG9uZ3NoZW5nLUI0MDUzNCB3cm90ZToNCj4gPj4+Pj4+PiArCXAgPSBvZl9nZXRf
cHJvcGVydHkobnAsICJhdmFpbGFibGUtcmFuZ2VzIiwgJmxlbik7DQo+ID4+Pj4+Pj4gKwlpZiAo
cCAmJiBsZW4gJSAoMiAqIHNpemVvZih1MzIpKSAhPSAwKSB7DQo+ID4+Pj4+Pj4gKwkJcHJfZXJy
KCIlczogbWFsZm9ybWVkIGZzbCxhdmFpbGFibGUtcmFuZ2VzIHByb3BlcnR5LlxuIiwNCj4gPj4+
Pj4+PiArCQkJCW5wLT5mdWxsX25hbWUpOw0KPiA+Pj4+Pj4+ICsJCXJldHVybiAtRUlOVkFMOw0K
PiA+Pj4+Pj4+ICsJfQ0KPiA+Pj4+Pj4NCj4gPj4+Pj4+IFlvdSBuZWVkIHRvIHN1cHBvcnQgZnNs
LGF2YWlsYWJsZS1yYW5nZXMgc2luY2UgdGhhdCdzIGluIGFuDQo+ID4+Pj4+PiBhY2NlcHRlZCBi
aW5kaW5nIGFuZCBwZW9wbGUgY291bGQgaGF2ZSBwYXJ0aXRpb25lZCBzZXR1cHMgYWxyZWFkeQ0K
PiA+PiB1c2luZyBpdC4NCj4gPj4+Pj4+DQo+ID4+Pj4+IFtXYW5nIERvbmdzaGVuZ10gRlNMIGNo
aXAgb3IgT1BFTi1QSUMgc3BlY2lmaWNhdGlvbihPbmx5IGEgZ3JvdXApDQo+ID4+Pj4+IGluIGVh
Y2ggZ3JvdXAgb25seSBmb3VyIHRpbWVyLiBUaGlzIGlzIHVuaWZpZWQuIFNvIGkgdXNlIGEgZ2Vu
ZXJpYw0KPiBuYW1lLg0KPiA+Pj4+PiBJIHRoaW5rIHRoZXJlIGlzIG5vdCBjb21wYXRpYmxlIHdp
dGggZXhpc3RpbmcgbXBpYyB0aW1lciBub2Rlcy4NCj4gPj4+Pg0KPiA+Pj4+IFdlIG5lZWQgdG8g
YmUgY29tcGF0aWJsZSB3aXRoIGV4aXN0aW5nIHRyZWVzLCBzbyB5b3UnZCBuZWVkIHRvDQo+ID4+
Pj4gY2hlY2sgZm9yIGJvdGggLS0gYnV0IEkgdGhpbmsgYW55IGZ1cnRoZXIgZGlzY3Vzc2lvbiBv
ZiB0aGUgZGV0YWlscw0KPiA+Pj4+IGlzIHByZW1hdHVyZSB1bnRpbCB3ZSBkZWNpZGUgd2hldGhl
ciB0aGlzIGlzIHdvcnRod2hpbGUgdG8gYmVnaW4NCj4gPj4+PiB3aXRoIChib3RoIHRoZSBzdXBw
b3J0IG9mIG5vbi1GU0wgdGltZXJzLCBhbmQgdGhlIGNyZWF0aW9uIG9mIGEgbmV3DQo+ID4+Pj4g
ZGV2aWNlIHRyZWUgYmluZGluZyB3aGljaCB3aWxsIG5vdCBiZSBpbXBsZW1lbnRlZCBieSBtYW55
IG9mIHRoZQ0KPiA+Pj4+IG1hY2hpbmVzIHRoYXQgaGF2ZSBub24tRlNMIG9wZW5waWMgYmVjYXVz
ZSB0aGV5IHJ1biByZWFsIE9wZW4NCj4gRmlybXdhcmUpLg0KPiA+Pj4+DQo+ID4+PiBbV2FuZyBE
b25nc2hlbmddDQo+ID4+PiAJcCA9IG9mX2dldF9wcm9wZXJ0eShucCwgImF2YWlsYWJsZS1yYW5n
ZXMiLCAmbGVuKTsNCj4gPj4+IAlpZiAoIXApDQo+ID4+PiAJCXAgPSBvZl9nZXRfcHJvcGVydHko
bnAsICJmc2wsYXZhaWxhYmxlLXJhbmdlcyIsICZsZW4pOw0KPiA+Pj4NCj4gPj4+IAl0aGlzIGNv
ZGUgYmUgY29tcGF0aWJsZSB3aXRoIGV4aXN0aW5nIHRyZWVzLg0KPiA+Pg0KPiA+PiBZZXMsIHRo
YXQncyB3aGF0IEkgbWVhbnQgYnkgY2hlY2tpbmcgYm90aC4NCj4gPj4NCj4gPj4gSSBzdGlsbCB0
aGluayB3ZSBuZWVkIHRvIGRpc2N1c3Mgd2h5IHdlJ3JlIGRvaW5nIHRoaXMgZmlyc3QuICBXaGF0
DQo+ID4+IHNwZWNpZmljIG1hY2hpbmVzIGFyZSBnb2luZyB0byBoYXZlIHRoZXNlIG5ldyBvcGVu
cGljIHRpbWVyIG5vZGVzPw0KPiA+Pg0KPiA+IFtXYW5nIERvbmdzaGVuZ10gSXQncyBzdXBwb3J0
IHRvIHBvd2VyIG1hbmFnZW1lbnQgYXdha2VuaW5nLiBBdA0KPiA+IHByZXNlbnQsIHRoZSBwb3dl
ciBtYW5hZ2VtZW50IG1vcmUgYW5kIG1vcmUgaW1wb3J0YW50LiBUaGlzIHdheSBpcw0KPiA+IGlt
cG9ydGFudCB0byB3YWtlIHVwIG1hY2hpbmUuIEF0IGxlYXN0IG5lZWQgc3VwcG9ydCBwb3dlciBt
YW5hZ2VtZW50DQo+ID4gb2YgbWFjaGluZSBzdGlsbCBuZWVkcyBzdWNoIGEgZHJpdmVyLg0KPiAN
Cj4gSSBtZWFuIHNwZWNpZmljYWxseSBmb3IgdGhlIG5vbi1GcmVlc2NhbGUgb3BlbnBpYyBub2Rl
cy4NCj4gDQpbV2FuZyBEb25nc2hlbmddIEkgdGhpbmsgbm9uLUZyZWVzY2FsZSBjaGlwcyBjYW4g
YWxzbyB1c2UgdGhpcyBmdW5jdGlvbg0KdG8gd2FrZSB1cCB0aGUgbWFjaGluZS4gQW5kIFRoZXJl
IGlzIGFsc28gYW4gaW1wb3J0YW50IGZlYXR1cmUsIEl0IGNhbiANCnBlcmlvZGljYWxseSBnZW5l
cmF0ZSBhbiBpbnRlcnJ1cHQuIEZvciBleGFtcGxlLCB0aGUgbmV0d29yayBwZXJpb2RpY2FsbHkN
CmNoZWNrIHRoZSBoYXJkd2FyZSBkZXZpY2UobGluayBzdGF0dXMpLg0KPiAtU2NvdHQNCg0K

Re: [PATCH v2 2/2] powerpc/mpic: add global timer support

[Scott Wood]

On 08/13/2012 09:32 PM, Wang Dongsheng-B40534 wrote:
> 
> 
>> -----Original Message-----
>> From: Wood Scott-B07421
>> Sent: Tuesday, August 14, 2012 10:19 AM
>> To: Wang Dongsheng-B40534
>> Cc: Wood Scott-B07421; benh@kernel.crashing.org; paulus@samba.org;
>> linuxppc-dev@lists.ozlabs.org; Gala Kumar-B11780; Li Yang-R58472
>> Subject: Re: [PATCH v2 2/2] powerpc/mpic: add global timer support
>>
>> On 08/13/2012 09:15 PM, Wang Dongsheng-B40534 wrote:
>>>
>>>
>>>> -----Original Message-----
>>>> From: Wood Scott-B07421
>>>> Sent: Tuesday, August 14, 2012 10:05 AM
>>>> To: Wang Dongsheng-B40534
>>>> Cc: Wood Scott-B07421; benh@kernel.crashing.org; paulus@samba.org;
>>>> linuxppc-dev@lists.ozlabs.org; Gala Kumar-B11780; Li Yang-R58472
>>>> Subject: Re: [PATCH v2 2/2] powerpc/mpic: add global timer support
>>>>
>>>> On 08/13/2012 09:00 PM, Wang Dongsheng-B40534 wrote:
>>>>>
>>>>>
>>>>>> -----Original Message-----
>>>>>> From: Wood Scott-B07421
>>>>>> Sent: Tuesday, August 14, 2012 1:37 AM
>>>>>> To: Wang Dongsheng-B40534
>>>>>> Cc: Wood Scott-B07421; benh@kernel.crashing.org; paulus@samba.org;
>>>>>> linuxppc-dev@lists.ozlabs.org; Gala Kumar-B11780; Li Yang-R58472
>>>>>> Subject: Re: [PATCH v2 2/2] powerpc/mpic: add global timer support
>>>>>>
>>>>>> On 08/13/2012 01:18 AM, Wang Dongsheng-B40534 wrote:
>>>>>>>>> +	p = of_get_property(np, "available-ranges", &len);
>>>>>>>>> +	if (p && len % (2 * sizeof(u32)) != 0) {
>>>>>>>>> +		pr_err("%s: malformed fsl,available-ranges property.\n",
>>>>>>>>> +				np->full_name);
>>>>>>>>> +		return -EINVAL;
>>>>>>>>> +	}
>>>>>>>>
>>>>>>>> You need to support fsl,available-ranges since that's in an
>>>>>>>> accepted binding and people could have partitioned setups already
>>>> using it.
>>>>>>>>
>>>>>>> [Wang Dongsheng] FSL chip or OPEN-PIC specification(Only a group)
>>>>>>> in each group only four timer. This is unified. So i use a generic
>> name.
>>>>>>> I think there is not compatible with existing mpic timer nodes.
>>>>>>
>>>>>> We need to be compatible with existing trees, so you'd need to
>>>>>> check for both -- but I think any further discussion of the details
>>>>>> is premature until we decide whether this is worthwhile to begin
>>>>>> with (both the support of non-FSL timers, and the creation of a new
>>>>>> device tree binding which will not be implemented by many of the
>>>>>> machines that have non-FSL openpic because they run real Open
>> Firmware).
>>>>>>
>>>>> [Wang Dongsheng]
>>>>> 	p = of_get_property(np, "available-ranges", &len);
>>>>> 	if (!p)
>>>>> 		p = of_get_property(np, "fsl,available-ranges", &len);
>>>>>
>>>>> 	this code be compatible with existing trees.
>>>>
>>>> Yes, that's what I meant by checking both.
>>>>
>>>> I still think we need to discuss why we're doing this first.  What
>>>> specific machines are going to have these new openpic timer nodes?
>>>>
>>> [Wang Dongsheng] It's support to power management awakening. At
>>> present, the power management more and more important. This way is
>>> important to wake up machine. At least need support power management
>>> of machine still needs such a driver.
>>
>> I mean specifically for the non-Freescale openpic nodes.
>>
> [Wang Dongsheng] I think non-Freescale chips can also use this function
> to wake up the machine. 

Maybe (it's very machine-specific what can be used as a wake source),
but what I asked was what specific machines could make use of this.
Name *one* machine for which these new openpic timer nodes will actually
be created.

> And There is also an important feature, It can
> periodically generate an interrupt.

That's not important at all.  We already have a way to do that using the
decrementer.

> For example, the network periodically check the hardware device(link status).

And it uses standard Linux software timers to do it.

-Scott