From: Benjamin Herrenschmidt <benh@kernel.crashing.org>
To: Scott Wood <scottwood@freescale.com>
Cc: linuxppc-dev@lists.ozlabs.org,
"Aneesh Kumar K.V" <aneesh.kumar@linux.vnet.ibm.com>
Subject: Re: [PATCH] powerpc: fix typo in PTRS_PER_PUD
Date: Thu, 13 Sep 2012 09:06:01 +1000 [thread overview]
Message-ID: <1347491161.2276.14.camel@pasglop> (raw)
In-Reply-To: <20120912230009.GA17226@buserror.net>
On Wed, 2012-09-12 at 18:00 -0500, Scott Wood wrote:
> PTRS_PER_PUD should be based on PUD_INDEX_SIZE, not PMD_INDEX_SIZE. We
> got away with it because PUD and PMD had the same index size, but this is
> no longer true with Aneesh's patchset to support a 46-bit user effective
> address space.
Ah, my typo :-) Cool, I'll make sure to apply that before Aneesh
patches.
Thanks,
Ben.
> Signed-off-by: Scott Wood <scottwood@freescale.com>
> ---
> arch/powerpc/include/asm/pgtable-ppc64-4k.h | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/arch/powerpc/include/asm/pgtable-ppc64-4k.h b/arch/powerpc/include/asm/pgtable-ppc64-4k.h
> index b3eccf2..12798c9 100644
> --- a/arch/powerpc/include/asm/pgtable-ppc64-4k.h
> +++ b/arch/powerpc/include/asm/pgtable-ppc64-4k.h
> @@ -19,7 +19,7 @@
>
> #define PTRS_PER_PTE (1 << PTE_INDEX_SIZE)
> #define PTRS_PER_PMD (1 << PMD_INDEX_SIZE)
> -#define PTRS_PER_PUD (1 << PMD_INDEX_SIZE)
> +#define PTRS_PER_PUD (1 << PUD_INDEX_SIZE)
> #define PTRS_PER_PGD (1 << PGD_INDEX_SIZE)
>
> /* PMD_SHIFT determines what a second-level page table entry can map */
prev parent reply other threads:[~2012-09-12 23:08 UTC|newest]
Thread overview: 2+ messages / expand[flat|nested] mbox.gz Atom feed top
2012-09-12 23:00 [PATCH] powerpc: fix typo in PTRS_PER_PUD Scott Wood
2012-09-12 23:06 ` Benjamin Herrenschmidt [this message]
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