From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mail1.windriver.com (mail1.windriver.com [147.11.146.13]) (using TLSv1 with cipher ECDHE-RSA-AES256-SHA (256/256 bits)) (Client CN "mail1.windriver.com", Issuer "Intel External Basic Issuing CA 3A" (not verified)) by ozlabs.org (Postfix) with ESMTPS id 936552C0083 for ; Mon, 17 Sep 2012 19:54:36 +1000 (EST) From: Tiejun Chen To: Subject: [v5][PATCH 1/3] powerpc/kprobe: introduce a new thread flag Date: Mon, 17 Sep 2012 17:54:29 +0800 Message-ID: <1347875671-15838-1-git-send-email-tiejun.chen@windriver.com> MIME-Version: 1.0 Content-Type: text/plain Cc: linuxppc-dev@lists.ozlabs.org List-Id: Linux on PowerPC Developers Mail List List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , We need to add a new thread flag, TIF_EMULATE_STACK_STORE, for emulating stack store operation while exiting exception. Signed-off-by: Tiejun Chen --- arch/powerpc/include/asm/thread_info.h | 3 +++ 1 file changed, 3 insertions(+) diff --git a/arch/powerpc/include/asm/thread_info.h b/arch/powerpc/include/asm/thread_info.h index e942203..8ceea14 100644 --- a/arch/powerpc/include/asm/thread_info.h +++ b/arch/powerpc/include/asm/thread_info.h @@ -104,6 +104,8 @@ static inline struct thread_info *current_thread_info(void) #define TIF_NOTIFY_RESUME 13 /* callback before returning to user */ #define TIF_UPROBE 14 /* breakpointed or single-stepping */ #define TIF_SYSCALL_TRACEPOINT 15 /* syscall tracepoint instrumentation */ +#define TIF_EMULATE_STACK_STORE 16 /* Is an instruction emulation + for stack store? */ /* as above, but as bit values */ #define _TIF_SYSCALL_TRACE (1<