From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from va3outboundpool.messaging.microsoft.com (va3ehsobe005.messaging.microsoft.com [216.32.180.31]) (using TLSv1 with cipher AES128-SHA (128/128 bits)) (Client CN "mail.global.frontbridge.com", Issuer "Microsoft Secure Server Authority" (not verified)) by ozlabs.org (Postfix) with ESMTPS id B42E92C0B87 for ; Mon, 18 Feb 2013 23:59:46 +1100 (EST) From: Varun Sethi To: , , , , , Subject: [PATCH 3/6] powerpc/fsl_pci: Added defines for the FSL PCI controller BRR1 register. Date: Mon, 18 Feb 2013 18:22:16 +0530 Message-ID: <1361191939-21260-4-git-send-email-Varun.Sethi@freescale.com> In-Reply-To: <1361191939-21260-1-git-send-email-Varun.Sethi@freescale.com> References: <1361191939-21260-1-git-send-email-Varun.Sethi@freescale.com> MIME-Version: 1.0 Content-Type: text/plain Cc: Varun Sethi List-Id: Linux on PowerPC Developers Mail List List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Macros for checking FSL PCI controller version. Signed-off-by: Varun Sethi --- arch/powerpc/include/asm/pci-bridge.h | 4 ++++ 1 files changed, 4 insertions(+), 0 deletions(-) diff --git a/arch/powerpc/include/asm/pci-bridge.h b/arch/powerpc/include/asm/pci-bridge.h index 025a130..c12ed78 100644 --- a/arch/powerpc/include/asm/pci-bridge.h +++ b/arch/powerpc/include/asm/pci-bridge.h @@ -14,6 +14,10 @@ struct device_node; +/* FSL PCI controller BRR1 register */ +#define PCI_FSL_BRR1 0xbf8 +#define PCI_FSL_BRR1_VER 0xffff + /* * Structure of a PCI controller (host bridge) */ -- 1.7.4.1