* [PATCH 0/3] powerpc: FSCR fixes for POWER8
@ 2013-03-04 9:46 Michael Neuling
2013-03-04 9:46 ` [PATCH 1/3] powerpc: Fix setting FSCR for HV=0 and secondary CPUs Michael Neuling
` (2 more replies)
0 siblings, 3 replies; 10+ messages in thread
From: Michael Neuling @ 2013-03-04 9:46 UTC (permalink / raw)
To: Benjamin Herrenschmidt; +Cc: Michael Neuling, linuxppc-dev, Ian Munsie
Benh,
Here are a few fixes for the POWER8 FSCR.
First patch changes the FSCR so that it's set on secondary CPUs as well as when
MSR HV=0.
Second two patches make sure that the FSCR DSCR bit is set so that we don't
trap on DSCR accesses.
These are aimed to fix issues in 3.9.
Mikey
^ permalink raw reply [flat|nested] 10+ messages in thread* [PATCH 1/3] powerpc: Fix setting FSCR for HV=0 and secondary CPUs 2013-03-04 9:46 [PATCH 0/3] powerpc: FSCR fixes for POWER8 Michael Neuling @ 2013-03-04 9:46 ` Michael Neuling 2013-03-05 5:06 ` Benjamin Herrenschmidt 2013-03-04 9:46 ` [PATCH 2/3] powerpc: Add DSCR FSCR register bit definition Michael Neuling 2013-03-04 9:46 ` [PATCH 3/3] powerpc: Set DSCR bit in FSCR setup Michael Neuling 2 siblings, 1 reply; 10+ messages in thread From: Michael Neuling @ 2013-03-04 9:46 UTC (permalink / raw) To: Benjamin Herrenschmidt; +Cc: Michael Neuling, linuxppc-dev, Ian Munsie Currently we only set the FSCR when HV=1 but this feature is available when HV=0 also. This patch sets FSCR when HV=0. Also, we currently only set the FSCR on the master CPU. This patch also sets the FSCR on secondary CPUs. Signed-off-by: Michael Neuling <mikey@neuling.org> cc: Ian Munsie <imunsie@au1.ibm.com> --- arch/powerpc/kernel/cpu_setup_power.S | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/arch/powerpc/kernel/cpu_setup_power.S b/arch/powerpc/kernel/cpu_setup_power.S index d29facb..bb2d203 100644 --- a/arch/powerpc/kernel/cpu_setup_power.S +++ b/arch/powerpc/kernel/cpu_setup_power.S @@ -48,6 +48,7 @@ _GLOBAL(__restore_cpu_power7) _GLOBAL(__setup_cpu_power8) mflr r11 + bl __init_FSCR bl __init_hvmode_206 mtlr r11 beqlr @@ -56,13 +57,13 @@ _GLOBAL(__setup_cpu_power8) mfspr r3,SPRN_LPCR oris r3, r3, LPCR_AIL_3@h bl __init_LPCR - bl __init_FSCR bl __init_TLB mtlr r11 blr _GLOBAL(__restore_cpu_power8) mflr r11 + bl __init_FSCR mfmsr r3 rldicl. r0,r3,4,63 beqlr -- 1.7.10.4 ^ permalink raw reply related [flat|nested] 10+ messages in thread
* Re: [PATCH 1/3] powerpc: Fix setting FSCR for HV=0 and secondary CPUs 2013-03-04 9:46 ` [PATCH 1/3] powerpc: Fix setting FSCR for HV=0 and secondary CPUs Michael Neuling @ 2013-03-05 5:06 ` Benjamin Herrenschmidt 2013-03-05 5:45 ` [PATCH 0/3] powerpc: FSCR fixes for POWER8 Michael Neuling 0 siblings, 1 reply; 10+ messages in thread From: Benjamin Herrenschmidt @ 2013-03-05 5:06 UTC (permalink / raw) To: Michael Neuling; +Cc: linuxppc-dev, Ian Munsie On Mon, 2013-03-04 at 20:46 +1100, Michael Neuling wrote: > Currently we only set the FSCR when HV=1 but this feature is available when > HV=0 also. This patch sets FSCR when HV=0. > > Also, we currently only set the FSCR on the master CPU. This patch also sets > the FSCR on secondary CPUs. Please add a quick blurb/reminder of what FSCR is (at least expand the accronym). Cheers, Ben. > Signed-off-by: Michael Neuling <mikey@neuling.org> > cc: Ian Munsie <imunsie@au1.ibm.com> > --- > arch/powerpc/kernel/cpu_setup_power.S | 3 ++- > 1 file changed, 2 insertions(+), 1 deletion(-) > > diff --git a/arch/powerpc/kernel/cpu_setup_power.S b/arch/powerpc/kernel/cpu_setup_power.S > index d29facb..bb2d203 100644 > --- a/arch/powerpc/kernel/cpu_setup_power.S > +++ b/arch/powerpc/kernel/cpu_setup_power.S > @@ -48,6 +48,7 @@ _GLOBAL(__restore_cpu_power7) > > _GLOBAL(__setup_cpu_power8) > mflr r11 > + bl __init_FSCR > bl __init_hvmode_206 > mtlr r11 > beqlr > @@ -56,13 +57,13 @@ _GLOBAL(__setup_cpu_power8) > mfspr r3,SPRN_LPCR > oris r3, r3, LPCR_AIL_3@h > bl __init_LPCR > - bl __init_FSCR > bl __init_TLB > mtlr r11 > blr > > _GLOBAL(__restore_cpu_power8) > mflr r11 > + bl __init_FSCR > mfmsr r3 > rldicl. r0,r3,4,63 > beqlr ^ permalink raw reply [flat|nested] 10+ messages in thread
* [PATCH 0/3] powerpc: FSCR fixes for POWER8 2013-03-05 5:06 ` Benjamin Herrenschmidt @ 2013-03-05 5:45 ` Michael Neuling 2013-03-05 5:45 ` [PATCH 1/3] powerpc: Fix setting FSCR for HV=0 and on secondary CPUs Michael Neuling ` (2 more replies) 0 siblings, 3 replies; 10+ messages in thread From: Michael Neuling @ 2013-03-05 5:45 UTC (permalink / raw) To: Benjamin Herrenschmidt; +Cc: Michael Neuling, linuxppc-dev, Ian Munsie Benh, Here are a few fixes for the POWER8 (Performance Optimization With Enhanced RISC Eight) FSCR (Facility Status & Control Register). First patch changes the FSCR so that it's set on secondary CPUs as well as when MSR HV=0. Second two patches make sure that the FSCR DSCR (Data Stream Control Register) bit is set so that we don't trap on DSCR usage. These are aimed to fix issues in 3.9. v2: Addressing comments from benh (Benjamin Herrenschmidt) Mikey ^ permalink raw reply [flat|nested] 10+ messages in thread
* [PATCH 1/3] powerpc: Fix setting FSCR for HV=0 and on secondary CPUs 2013-03-05 5:45 ` [PATCH 0/3] powerpc: FSCR fixes for POWER8 Michael Neuling @ 2013-03-05 5:45 ` Michael Neuling 2013-03-05 5:45 ` [PATCH 2/3] powerpc: Add DSCR FSCR register bit definition Michael Neuling 2013-03-05 5:45 ` [PATCH 3/3] powerpc: Set DSCR bit in FSCR setup Michael Neuling 2 siblings, 0 replies; 10+ messages in thread From: Michael Neuling @ 2013-03-05 5:45 UTC (permalink / raw) To: Benjamin Herrenschmidt; +Cc: Michael Neuling, linuxppc-dev, Ian Munsie Currently we only set the FSCR (Facility Status and Control Register) when HV=1 but this feature is available when HV=0 also. This patch sets FSCR when HV=0. Also, we currently only set the FSCR on the master CPU. This patch also sets the FSCR on secondary CPUs. Signed-off-by: Michael Neuling <mikey@neuling.org> cc: Ian Munsie <imunsie@au1.ibm.com> --- arch/powerpc/kernel/cpu_setup_power.S | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/arch/powerpc/kernel/cpu_setup_power.S b/arch/powerpc/kernel/cpu_setup_power.S index d29facb..bb2d203 100644 --- a/arch/powerpc/kernel/cpu_setup_power.S +++ b/arch/powerpc/kernel/cpu_setup_power.S @@ -48,6 +48,7 @@ _GLOBAL(__restore_cpu_power7) _GLOBAL(__setup_cpu_power8) mflr r11 + bl __init_FSCR bl __init_hvmode_206 mtlr r11 beqlr @@ -56,13 +57,13 @@ _GLOBAL(__setup_cpu_power8) mfspr r3,SPRN_LPCR oris r3, r3, LPCR_AIL_3@h bl __init_LPCR - bl __init_FSCR bl __init_TLB mtlr r11 blr _GLOBAL(__restore_cpu_power8) mflr r11 + bl __init_FSCR mfmsr r3 rldicl. r0,r3,4,63 beqlr -- 1.7.10.4 ^ permalink raw reply related [flat|nested] 10+ messages in thread
* [PATCH 2/3] powerpc: Add DSCR FSCR register bit definition 2013-03-05 5:45 ` [PATCH 0/3] powerpc: FSCR fixes for POWER8 Michael Neuling 2013-03-05 5:45 ` [PATCH 1/3] powerpc: Fix setting FSCR for HV=0 and on secondary CPUs Michael Neuling @ 2013-03-05 5:45 ` Michael Neuling 2013-03-05 5:45 ` [PATCH 3/3] powerpc: Set DSCR bit in FSCR setup Michael Neuling 2 siblings, 0 replies; 10+ messages in thread From: Michael Neuling @ 2013-03-05 5:45 UTC (permalink / raw) To: Benjamin Herrenschmidt; +Cc: Michael Neuling, linuxppc-dev, Ian Munsie This sets the DSCR (Data Stream Control Register) in the FSCR (Facility Status & Control Register). Also harmonise TAR (Target Address Register) FSCR bit definition too. Signed-off-by: Michael Neuling <mikey@neuling.org> --- arch/powerpc/include/asm/reg.h | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/arch/powerpc/include/asm/reg.h b/arch/powerpc/include/asm/reg.h index e665861..c9c67fc 100644 --- a/arch/powerpc/include/asm/reg.h +++ b/arch/powerpc/include/asm/reg.h @@ -266,7 +266,8 @@ #define SPRN_HSRR0 0x13A /* Hypervisor Save/Restore 0 */ #define SPRN_HSRR1 0x13B /* Hypervisor Save/Restore 1 */ #define SPRN_FSCR 0x099 /* Facility Status & Control Register */ -#define FSCR_TAR (1<<8) /* Enable Target Adress Register */ +#define FSCR_TAR (1 << (63-55)) /* Enable Target Address Register */ +#define FSCR_DSCR (1 << (63-61)) /* Enable Data Stream Control Register */ #define SPRN_TAR 0x32f /* Target Address Register */ #define SPRN_LPCR 0x13E /* LPAR Control Register */ #define LPCR_VPM0 (1ul << (63-0)) -- 1.7.10.4 ^ permalink raw reply related [flat|nested] 10+ messages in thread
* [PATCH 3/3] powerpc: Set DSCR bit in FSCR setup 2013-03-05 5:45 ` [PATCH 0/3] powerpc: FSCR fixes for POWER8 Michael Neuling 2013-03-05 5:45 ` [PATCH 1/3] powerpc: Fix setting FSCR for HV=0 and on secondary CPUs Michael Neuling 2013-03-05 5:45 ` [PATCH 2/3] powerpc: Add DSCR FSCR register bit definition Michael Neuling @ 2013-03-05 5:45 ` Michael Neuling 2 siblings, 0 replies; 10+ messages in thread From: Michael Neuling @ 2013-03-05 5:45 UTC (permalink / raw) To: Benjamin Herrenschmidt; +Cc: Michael Neuling, linuxppc-dev, Ian Munsie We support DSCR (Data Stream Control Register) so we should make sure we set it in the FSCR (Facility Status & Control Register) incase some firmwares don't set it. If we don't set this, we'll take a facility unavailable exception when using the DSCR. Signed-off-by: Michael Neuling <mikey@neuling.org> --- arch/powerpc/kernel/cpu_setup_power.S | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/powerpc/kernel/cpu_setup_power.S b/arch/powerpc/kernel/cpu_setup_power.S index bb2d203..ea847ab 100644 --- a/arch/powerpc/kernel/cpu_setup_power.S +++ b/arch/powerpc/kernel/cpu_setup_power.S @@ -116,7 +116,7 @@ __init_LPCR: __init_FSCR: mfspr r3,SPRN_FSCR - ori r3,r3,FSCR_TAR + ori r3,r3,FSCR_TAR|FSCR_DSCR mtspr SPRN_FSCR,r3 blr -- 1.7.10.4 ^ permalink raw reply related [flat|nested] 10+ messages in thread
* [PATCH 2/3] powerpc: Add DSCR FSCR register bit definition 2013-03-04 9:46 [PATCH 0/3] powerpc: FSCR fixes for POWER8 Michael Neuling 2013-03-04 9:46 ` [PATCH 1/3] powerpc: Fix setting FSCR for HV=0 and secondary CPUs Michael Neuling @ 2013-03-04 9:46 ` Michael Neuling 2013-03-05 5:09 ` Benjamin Herrenschmidt 2013-03-04 9:46 ` [PATCH 3/3] powerpc: Set DSCR bit in FSCR setup Michael Neuling 2 siblings, 1 reply; 10+ messages in thread From: Michael Neuling @ 2013-03-04 9:46 UTC (permalink / raw) To: Benjamin Herrenschmidt; +Cc: Michael Neuling, linuxppc-dev, Ian Munsie Also harmonise TAR bit definition too. Signed-off-by: Michael Neuling <mikey@neuling.org> --- arch/powerpc/include/asm/reg.h | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/arch/powerpc/include/asm/reg.h b/arch/powerpc/include/asm/reg.h index e665861..a43cd2d 100644 --- a/arch/powerpc/include/asm/reg.h +++ b/arch/powerpc/include/asm/reg.h @@ -266,7 +266,8 @@ #define SPRN_HSRR0 0x13A /* Hypervisor Save/Restore 0 */ #define SPRN_HSRR1 0x13B /* Hypervisor Save/Restore 1 */ #define SPRN_FSCR 0x099 /* Facility Status & Control Register */ -#define FSCR_TAR (1<<8) /* Enable Target Adress Register */ +#define FSCR_TAR (1 << (63-55)) /* Enable Target Adress Register */ +#define FSCR_DSCR (1 << (63-61)) /* Enable DSCR */ #define SPRN_TAR 0x32f /* Target Address Register */ #define SPRN_LPCR 0x13E /* LPAR Control Register */ #define LPCR_VPM0 (1ul << (63-0)) -- 1.7.10.4 ^ permalink raw reply related [flat|nested] 10+ messages in thread
* Re: [PATCH 2/3] powerpc: Add DSCR FSCR register bit definition 2013-03-04 9:46 ` [PATCH 2/3] powerpc: Add DSCR FSCR register bit definition Michael Neuling @ 2013-03-05 5:09 ` Benjamin Herrenschmidt 0 siblings, 0 replies; 10+ messages in thread From: Benjamin Herrenschmidt @ 2013-03-05 5:09 UTC (permalink / raw) To: Michael Neuling; +Cc: linuxppc-dev, Ian Munsie On Mon, 2013-03-04 at 20:46 +1100, Michael Neuling wrote: > Also harmonise TAR bit definition too. Same, expand accronyms, minimum blurb about what these are about (not a long explanation, just so that when I come out of the blue I can at least connect it to something that makes sense :-) Cheers, Ben. ^ permalink raw reply [flat|nested] 10+ messages in thread
* [PATCH 3/3] powerpc: Set DSCR bit in FSCR setup 2013-03-04 9:46 [PATCH 0/3] powerpc: FSCR fixes for POWER8 Michael Neuling 2013-03-04 9:46 ` [PATCH 1/3] powerpc: Fix setting FSCR for HV=0 and secondary CPUs Michael Neuling 2013-03-04 9:46 ` [PATCH 2/3] powerpc: Add DSCR FSCR register bit definition Michael Neuling @ 2013-03-04 9:46 ` Michael Neuling 2 siblings, 0 replies; 10+ messages in thread From: Michael Neuling @ 2013-03-04 9:46 UTC (permalink / raw) To: Benjamin Herrenschmidt; +Cc: Michael Neuling, linuxppc-dev, Ian Munsie We support DSCR so we should make sure we set it in the FSCR incase some firmwares don't set it. Signed-off-by: Michael Neuling <mikey@neuling.org> --- arch/powerpc/kernel/cpu_setup_power.S | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/powerpc/kernel/cpu_setup_power.S b/arch/powerpc/kernel/cpu_setup_power.S index bb2d203..ea847ab 100644 --- a/arch/powerpc/kernel/cpu_setup_power.S +++ b/arch/powerpc/kernel/cpu_setup_power.S @@ -116,7 +116,7 @@ __init_LPCR: __init_FSCR: mfspr r3,SPRN_FSCR - ori r3,r3,FSCR_TAR + ori r3,r3,FSCR_TAR|FSCR_DSCR mtspr SPRN_FSCR,r3 blr -- 1.7.10.4 ^ permalink raw reply related [flat|nested] 10+ messages in thread
end of thread, other threads:[~2013-03-05 5:45 UTC | newest] Thread overview: 10+ messages (download: mbox.gz follow: Atom feed -- links below jump to the message on this page -- 2013-03-04 9:46 [PATCH 0/3] powerpc: FSCR fixes for POWER8 Michael Neuling 2013-03-04 9:46 ` [PATCH 1/3] powerpc: Fix setting FSCR for HV=0 and secondary CPUs Michael Neuling 2013-03-05 5:06 ` Benjamin Herrenschmidt 2013-03-05 5:45 ` [PATCH 0/3] powerpc: FSCR fixes for POWER8 Michael Neuling 2013-03-05 5:45 ` [PATCH 1/3] powerpc: Fix setting FSCR for HV=0 and on secondary CPUs Michael Neuling 2013-03-05 5:45 ` [PATCH 2/3] powerpc: Add DSCR FSCR register bit definition Michael Neuling 2013-03-05 5:45 ` [PATCH 3/3] powerpc: Set DSCR bit in FSCR setup Michael Neuling 2013-03-04 9:46 ` [PATCH 2/3] powerpc: Add DSCR FSCR register bit definition Michael Neuling 2013-03-05 5:09 ` Benjamin Herrenschmidt 2013-03-04 9:46 ` [PATCH 3/3] powerpc: Set DSCR bit in FSCR setup Michael Neuling
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