From: "Aneesh Kumar K.V" <aneesh.kumar@linux.vnet.ibm.com>
To: benh@kernel.crashing.org, paulus@samba.org
Cc: linuxppc-dev@lists.ozlabs.org,
"Aneesh Kumar K.V" <aneesh.kumar@linux.vnet.ibm.com>
Subject: [PATCH -V2 13/26] powerpc: Update tlbie/tlbiel as per ISA doc
Date: Wed, 6 Mar 2013 11:40:14 +0530 [thread overview]
Message-ID: <1362550227-575-14-git-send-email-aneesh.kumar@linux.vnet.ibm.com> (raw)
In-Reply-To: <1362550227-575-1-git-send-email-aneesh.kumar@linux.vnet.ibm.com>
From: "Aneesh Kumar K.V" <aneesh.kumar@linux.vnet.ibm.com>
This make sure we handle multiple page size segment correctly.
Signed-off-by: Aneesh Kumar K.V <aneesh.kumar@linux.vnet.ibm.com>
---
arch/powerpc/mm/hash_native_64.c | 52 +++++++++++++++++++++++++++++---------
1 file changed, 40 insertions(+), 12 deletions(-)
diff --git a/arch/powerpc/mm/hash_native_64.c b/arch/powerpc/mm/hash_native_64.c
index 5e7f45c..f106fa4 100644
--- a/arch/powerpc/mm/hash_native_64.c
+++ b/arch/powerpc/mm/hash_native_64.c
@@ -39,7 +39,7 @@
DEFINE_RAW_SPINLOCK(native_tlbie_lock);
-static inline void __tlbie(unsigned long vpn, int psize, int apsize, int ssize)
+static inline void __tlbie(unsigned long vpn, int bpsize, int apsize, int ssize)
{
unsigned long va;
unsigned int penc;
@@ -59,19 +59,33 @@ static inline void __tlbie(unsigned long vpn, int psize, int apsize, int ssize)
*/
va &= ~(0xffffULL << 48);
- switch (psize) {
+ switch (bpsize) {
case MMU_PAGE_4K:
+ /* clear out bits after (52) [0....52.....63] */
+ va &= ~((1ul << (64 - 52)) - 1);
va |= ssize << 8;
+ va |= mmu_psize_defs[apsize].sllp << 6;
asm volatile(ASM_FTR_IFCLR("tlbie %0,0", PPC_TLBIE(%1,%0), %2)
: : "r" (va), "r"(0), "i" (CPU_FTR_ARCH_206)
: "memory");
break;
default:
/* We need 14 to 14 + i bits of va */
- penc = mmu_psize_defs[psize].penc[apsize];
- va &= ~((1ul << mmu_psize_defs[psize].shift) - 1);
+ penc = mmu_psize_defs[bpsize].penc[apsize];
+ /* clear out bits after (44) [0....44.....63] */
+ va &= ~((1ul << (64 - 44)) - 1);
va |= penc << 12;
va |= ssize << 8;
+ /* Add AVAL part */
+ if (bpsize != apsize) {
+ /*
+ * MPSS, 64K base page size and 16MB parge page size
+ * We don't need all the bits, but this seems to work.
+ * vpn cover upto 65 bits of va. (0...65) and we need
+ * 56..62 bits of va.
+ */
+ va |= ((vpn >> 2) & 0xfe);
+ }
va |= 1; /* L */
asm volatile(ASM_FTR_IFCLR("tlbie %0,1", PPC_TLBIE(%1,%0), %2)
: : "r" (va), "r"(0), "i" (CPU_FTR_ARCH_206)
@@ -80,7 +94,7 @@ static inline void __tlbie(unsigned long vpn, int psize, int apsize, int ssize)
}
}
-static inline void __tlbiel(unsigned long vpn, int psize, int apsize, int ssize)
+static inline void __tlbiel(unsigned long vpn, int bpsize, int apsize, int ssize)
{
unsigned long va;
unsigned int penc;
@@ -94,18 +108,32 @@ static inline void __tlbiel(unsigned long vpn, int psize, int apsize, int ssize)
*/
va &= ~(0xffffULL << 48);
- switch (psize) {
+ switch (bpsize) {
case MMU_PAGE_4K:
+ /* clear out bits after(52) [0....52.....63] */
+ va &= ~((1ul << (64 - 52)) - 1);
va |= ssize << 8;
+ va |= mmu_psize_defs[apsize].sllp << 6;
asm volatile(".long 0x7c000224 | (%0 << 11) | (0 << 21)"
: : "r"(va) : "memory");
break;
default:
/* We need 14 to 14 + i bits of va */
- penc = mmu_psize_defs[psize].penc[apsize];
- va &= ~((1ul << mmu_psize_defs[psize].shift) - 1);
+ penc = mmu_psize_defs[bpsize].penc[apsize];
+ /* clear out bits after(44) [0....44.....63] */
+ va &= ~((1ul << (64 - 44)) - 1);
va |= penc << 12;
va |= ssize << 8;
+ /* Add AVAL part */
+ if (bpsize != apsize) {
+ /*
+ * MPSS, 64K base page size and 16MB parge page size
+ * We don't need all the bits, but this seems to work.
+ * vpn cover upto 65 bits of va. (0...65) and we need
+ * 56..62 bits of va.
+ */
+ va |= ((vpn >> 2) & 0xfe);
+ }
va |= 1; /* L */
asm volatile(".long 0x7c000224 | (%0 << 11) | (1 << 21)"
: : "r"(va) : "memory");
@@ -114,22 +142,22 @@ static inline void __tlbiel(unsigned long vpn, int psize, int apsize, int ssize)
}
-static inline void tlbie(unsigned long vpn, int psize, int apsize,
+static inline void tlbie(unsigned long vpn, int bpsize, int apsize,
int ssize, int local)
{
unsigned int use_local = local && mmu_has_feature(MMU_FTR_TLBIEL);
int lock_tlbie = !mmu_has_feature(MMU_FTR_LOCKLESS_TLBIE);
if (use_local)
- use_local = mmu_psize_defs[psize].tlbiel;
+ use_local = mmu_psize_defs[bpsize].tlbiel;
if (lock_tlbie && !use_local)
raw_spin_lock(&native_tlbie_lock);
asm volatile("ptesync": : :"memory");
if (use_local) {
- __tlbiel(vpn, psize, apsize, ssize);
+ __tlbiel(vpn, bpsize, apsize, ssize);
asm volatile("ptesync": : :"memory");
} else {
- __tlbie(vpn, psize, apsize, ssize);
+ __tlbie(vpn, bpsize, apsize, ssize);
asm volatile("eieio; tlbsync; ptesync": : :"memory");
}
if (lock_tlbie && !use_local)
--
1.7.10
next prev parent reply other threads:[~2013-03-06 6:11 UTC|newest]
Thread overview: 33+ messages / expand[flat|nested] mbox.gz Atom feed top
2013-03-06 6:10 [PATCH -V2 00/26]T HP support for PPC64 Aneesh Kumar K.V
2013-03-06 6:10 ` [PATCH -V2 01/26] powerpc: Use signed formatting when printing error Aneesh Kumar K.V
2013-03-06 6:10 ` [PATCH -V2 02/26] powerpc: Save DAR and DSISR in pt_regs on MCE Aneesh Kumar K.V
2013-03-06 6:10 ` [PATCH -V2 03/26] powerpc: Don't hard code the size of pte page Aneesh Kumar K.V
2013-03-06 6:10 ` [PATCH -V2 04/26] powerpc: Reduce the PTE_INDEX_SIZE Aneesh Kumar K.V
2013-03-06 6:10 ` [PATCH -V2 05/26] powerpc: Move the pte free routines from common header Aneesh Kumar K.V
2013-03-06 6:10 ` [PATCH -V2 06/26] powerpc: Reduce PTE table memory wastage Aneesh Kumar K.V
2013-03-06 6:10 ` [PATCH -V2 07/26] powerpc: Add size argument to pgtable_cache_add Aneesh Kumar K.V
2013-03-13 2:47 ` Paul Mackerras
2013-03-13 9:25 ` Aneesh Kumar K.V
2013-03-13 11:34 ` Paul Mackerras
2013-03-06 6:10 ` [PATCH -V2 08/26] powerpc: Clarify __pgtable_cache_add by renaming shift to index Aneesh Kumar K.V
2013-03-06 6:10 ` [PATCH -V2 09/26] powerpc: Use encode avpn where we need only avpn values Aneesh Kumar K.V
2013-03-06 6:10 ` [PATCH -V2 10/26] powerpc: Decode the pte-lp-encoding bits correctly Aneesh Kumar K.V
2013-03-13 4:09 ` Paul Mackerras
2013-03-06 6:10 ` [PATCH -V2 11/26] powerpc: Fix hpte_decode to use the correct decoding for page sizes Aneesh Kumar K.V
2013-03-13 2:56 ` Paul Mackerras
2013-03-06 6:10 ` [PATCH -V2 12/26] powerpc: Return all the valid pte ecndoing in KVM_PPC_GET_SMMU_INFO ioctl Aneesh Kumar K.V
2013-03-13 4:11 ` Paul Mackerras
2013-03-06 6:10 ` Aneesh Kumar K.V [this message]
2013-03-06 6:10 ` [PATCH -V2 14/26] powerpc: print both base and actual page size on hash failure Aneesh Kumar K.V
2013-03-06 6:10 ` [PATCH -V2 15/26] powerpc: Print page size info during boot Aneesh Kumar K.V
2013-03-06 6:10 ` [PATCH -V2 16/26] mm/THP: HPAGE_SHIFT is not a #define on some arch Aneesh Kumar K.V
2013-03-06 6:10 ` [PATCH -V2 17/26] mm/THP: Add pmd args to pgtable deposit and withdraw APIs Aneesh Kumar K.V
2013-03-06 6:10 ` [PATCH -V2 18/26] mm/THP: withdraw the pgtable after pmdp related operations Aneesh Kumar K.V
2013-03-06 6:10 ` [PATCH -V2 19/26] powerpc/THP: Implement transparent huge pages for ppc64 Aneesh Kumar K.V
2013-03-06 6:10 ` [PATCH -V2 20/26] powerpc/THP: Differentiate THP PMD entries from HUGETLB PMD entries Aneesh Kumar K.V
2013-03-06 6:10 ` [PATCH -V2 21/26] powerpc/THP: Add code to handle HPTE faults for large pages Aneesh Kumar K.V
2013-03-06 6:10 ` [PATCH -V2 22/26] powerpc: Handle huge page in perf callchain Aneesh Kumar K.V
2013-03-06 6:10 ` [PATCH -V2 23/26] powerpc/THP: hypervisor require few WIMG bit set Aneesh Kumar K.V
2013-03-06 6:10 ` [PATCH -V2 24/26] powerpc/THP: get_user_pages_fast changes Aneesh Kumar K.V
2013-03-06 6:10 ` [PATCH -V2 25/26] powerpc/THP: Enable THP on PPC64 Aneesh Kumar K.V
2013-03-06 6:10 ` [PATCH -V2 26/26] powerpc: Optimize hugepage invalidate Aneesh Kumar K.V
Reply instructions:
You may reply publicly to this message via plain-text email
using any one of the following methods:
* Save the following mbox file, import it into your mail client,
and reply-to-all from there: mbox
Avoid top-posting and favor interleaved quoting:
https://en.wikipedia.org/wiki/Posting_style#Interleaved_style
* Reply using the --to, --cc, and --in-reply-to
switches of git-send-email(1):
git send-email \
--in-reply-to=1362550227-575-14-git-send-email-aneesh.kumar@linux.vnet.ibm.com \
--to=aneesh.kumar@linux.vnet.ibm.com \
--cc=benh@kernel.crashing.org \
--cc=linuxppc-dev@lists.ozlabs.org \
--cc=paulus@samba.org \
/path/to/YOUR_REPLY
https://kernel.org/pub/software/scm/git/docs/git-send-email.html
* If your mail client supports setting the In-Reply-To header
via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line
before the message body.
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox;
as well as URLs for NNTP newsgroup(s).