From: "Aneesh Kumar K.V" <aneesh.kumar@linux.vnet.ibm.com>
To: benh@kernel.crashing.org, paulus@samba.org
Cc: linuxppc-dev@lists.ozlabs.org,
"Aneesh Kumar K.V" <aneesh.kumar@linux.vnet.ibm.com>
Subject: [PATCH -V3 11/25] powerpc: Update tlbie/tlbiel as per ISA doc
Date: Fri, 15 Mar 2013 15:09:53 +0530 [thread overview]
Message-ID: <1363340407-22619-12-git-send-email-aneesh.kumar@linux.vnet.ibm.com> (raw)
In-Reply-To: <1363340407-22619-1-git-send-email-aneesh.kumar@linux.vnet.ibm.com>
From: "Aneesh Kumar K.V" <aneesh.kumar@linux.vnet.ibm.com>
This make sure we handle multiple page size segment correctly.
Signed-off-by: Aneesh Kumar K.V <aneesh.kumar@linux.vnet.ibm.com>
---
arch/powerpc/mm/hash_native_64.c | 32 ++++++++++++++++++++++++++++++--
1 file changed, 30 insertions(+), 2 deletions(-)
diff --git a/arch/powerpc/mm/hash_native_64.c b/arch/powerpc/mm/hash_native_64.c
index af9eb1c..409c916 100644
--- a/arch/powerpc/mm/hash_native_64.c
+++ b/arch/powerpc/mm/hash_native_64.c
@@ -61,7 +61,10 @@ static inline void __tlbie(unsigned long vpn, int psize, int apsize, int ssize)
switch (psize) {
case MMU_PAGE_4K:
+ /* clear out bits after (52) [0....52.....63] */
+ va &= ~((1ul << (64 - 52)) - 1);
va |= ssize << 8;
+ va |= mmu_psize_defs[apsize].sllp << 6;
asm volatile(ASM_FTR_IFCLR("tlbie %0,0", PPC_TLBIE(%1,%0), %2)
: : "r" (va), "r"(0), "i" (CPU_FTR_ARCH_206)
: "memory");
@@ -69,9 +72,20 @@ static inline void __tlbie(unsigned long vpn, int psize, int apsize, int ssize)
default:
/* We need 14 to 14 + i bits of va */
penc = mmu_psize_defs[psize].penc[apsize];
- va &= ~((1ul << mmu_psize_defs[psize].shift) - 1);
+ /* clear out bits after (44) [0....44.....63] */
+ va &= ~((1ul << (64 - 44)) - 1);
va |= penc << 12;
va |= ssize << 8;
+ /* Add AVAL part */
+ if (psize != apsize) {
+ /*
+ * MPSS, 64K base page size and 16MB parge page size
+ * We don't need all the bits, but this seems to work.
+ * vpn cover upto 65 bits of va. (0...65) and we need
+ * 56..62 bits of va.
+ */
+ va |= ((vpn >> 2) & 0xfe);
+ }
va |= 1; /* L */
asm volatile(ASM_FTR_IFCLR("tlbie %0,1", PPC_TLBIE(%1,%0), %2)
: : "r" (va), "r"(0), "i" (CPU_FTR_ARCH_206)
@@ -96,16 +110,30 @@ static inline void __tlbiel(unsigned long vpn, int psize, int apsize, int ssize)
switch (psize) {
case MMU_PAGE_4K:
+ /* clear out bits after(52) [0....52.....63] */
+ va &= ~((1ul << (64 - 52)) - 1);
va |= ssize << 8;
+ va |= mmu_psize_defs[apsize].sllp << 6;
asm volatile(".long 0x7c000224 | (%0 << 11) | (0 << 21)"
: : "r"(va) : "memory");
break;
default:
/* We need 14 to 14 + i bits of va */
penc = mmu_psize_defs[psize].penc[apsize];
- va &= ~((1ul << mmu_psize_defs[psize].shift) - 1);
+ /* clear out bits after(44) [0....44.....63] */
+ va &= ~((1ul << (64 - 44)) - 1);
va |= penc << 12;
va |= ssize << 8;
+ /* Add AVAL part */
+ if (psize != apsize) {
+ /*
+ * MPSS, 64K base page size and 16MB parge page size
+ * We don't need all the bits, but this seems to work.
+ * vpn cover upto 65 bits of va. (0...65) and we need
+ * 56..62 bits of va.
+ */
+ va |= ((vpn >> 2) & 0xfe);
+ }
va |= 1; /* L */
asm volatile(".long 0x7c000224 | (%0 << 11) | (1 << 21)"
: : "r"(va) : "memory");
--
1.7.10
next prev parent reply other threads:[~2013-03-15 9:40 UTC|newest]
Thread overview: 26+ messages / expand[flat|nested] mbox.gz Atom feed top
2013-03-15 9:39 [PATCH -V3 00/25] THP support for PPC64 Aneesh Kumar K.V
2013-03-15 9:39 ` [PATCH -V3 01/25] powerpc: Use signed formatting when printing error Aneesh Kumar K.V
2013-03-15 9:39 ` [PATCH -V3 02/25] powerpc: Save DAR and DSISR in pt_regs on MCE Aneesh Kumar K.V
2013-03-15 9:39 ` [PATCH -V3 03/25] powerpc: Don't hard code the size of pte page Aneesh Kumar K.V
2013-03-15 9:39 ` [PATCH -V3 04/25] powerpc: Reduce the PTE_INDEX_SIZE Aneesh Kumar K.V
2013-03-15 9:39 ` [PATCH -V3 05/25] powerpc: Move the pte free routines from common header Aneesh Kumar K.V
2013-03-15 9:39 ` [PATCH -V3 06/25] powerpc: Reduce PTE table memory wastage Aneesh Kumar K.V
2013-03-15 9:39 ` [PATCH -V3 07/25] powerpc: Use encode avpn where we need only avpn values Aneesh Kumar K.V
2013-03-15 9:39 ` [PATCH -V3 08/25] powerpc: Decode the pte-lp-encoding bits correctly Aneesh Kumar K.V
2013-03-15 9:39 ` [PATCH -V3 09/25] powerpc: Fix hpte_decode to use the correct decoding for page sizes Aneesh Kumar K.V
2013-03-15 9:39 ` [PATCH -V3 10/25] powerpc: Return all the valid pte ecndoing in KVM_PPC_GET_SMMU_INFO ioctl Aneesh Kumar K.V
2013-03-15 9:39 ` Aneesh Kumar K.V [this message]
2013-03-15 9:39 ` [PATCH -V3 12/25] powerpc: print both base and actual page size on hash failure Aneesh Kumar K.V
2013-03-15 9:39 ` [PATCH -V3 13/25] powerpc: Print page size info during boot Aneesh Kumar K.V
2013-03-15 9:39 ` [PATCH -V3 14/25] mm/THP: HPAGE_SHIFT is not a #define on some arch Aneesh Kumar K.V
2013-03-15 9:39 ` [PATCH -V3 15/25] mm/THP: Add pmd args to pgtable deposit and withdraw APIs Aneesh Kumar K.V
2013-03-15 9:39 ` [PATCH -V3 16/25] mm/THP: withdraw the pgtable after pmdp related operations Aneesh Kumar K.V
2013-03-15 9:39 ` [PATCH -V3 17/25] powerpc/THP: Implement transparent hugepages for ppc64 Aneesh Kumar K.V
2013-03-15 9:40 ` [PATCH -V3 18/25] powerpc/THP: Double the PMD table size for THP Aneesh Kumar K.V
2013-03-15 9:40 ` [PATCH -V3 19/25] powerpc/THP: Differentiate THP PMD entries from HUGETLB PMD entries Aneesh Kumar K.V
2013-03-15 9:40 ` [PATCH -V3 20/25] powerpc/THP: Add code to handle HPTE faults for large pages Aneesh Kumar K.V
2013-03-15 9:40 ` [PATCH -V3 21/25] powerpc: Handle hugepage in perf callchain Aneesh Kumar K.V
2013-03-15 9:40 ` [PATCH -V3 22/25] powerpc/THP: get_user_pages_fast changes Aneesh Kumar K.V
2013-03-15 9:40 ` [PATCH -V3 23/25] powerpc/THP: Enable THP on PPC64 Aneesh Kumar K.V
2013-03-15 9:40 ` [PATCH -V3 24/25] powerpc: Optimize hugepage invalidate Aneesh Kumar K.V
2013-03-15 9:40 ` [PATCH -V3 25/25] powerpc: Handle hugepages in kvm Aneesh Kumar K.V
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