From: Scott Wood <scottwood@freescale.com>
To: Mihai Caraman <mihai.caraman@freescale.com>
Cc: Mihai Caraman <mihai.caraman@freescale.com>,
linuxppc-dev@lists.ozlabs.org, kvm@vger.kernel.org,
kvm-ppc@vger.kernel.org
Subject: Re: [PATCH] KVM: PPC: e500: Expose MMU registers via ONE_REG
Date: Tue, 19 Mar 2013 12:26:25 -0500 [thread overview]
Message-ID: <1363713985.16671.12@snotra> (raw)
In-Reply-To: <1363713431-27926-1-git-send-email-mihai.caraman@freescale.com> (from mihai.caraman@freescale.com on Tue Mar 19 12:17:11 2013)
On 03/19/2013 12:17:11 PM, Mihai Caraman wrote:
> diff --git a/arch/powerpc/kvm/e500_mmu.c b/arch/powerpc/kvm/e500_mmu.c
> index 66b6e31..b77b855 100644
> --- a/arch/powerpc/kvm/e500_mmu.c
> +++ b/arch/powerpc/kvm/e500_mmu.c
> @@ -596,6 +596,95 @@ int kvmppc_set_sregs_e500_tlb(struct kvm_vcpu =20
> *vcpu, struct kvm_sregs *sregs)
> return 0;
> }
>=20
> +int kvmppc_get_one_reg_500_tlb(struct kvm_vcpu *vcpu, u64 id,
> + union kvmppc_one_reg *val)
s/500/e500/
> +int kvmppc_set_one_reg_500_tlb(struct kvm_vcpu *vcpu, u64 id,
> + union kvmppc_one_reg *val)
> +{
> + int r =3D 0;
> + long int i;
> +
> + switch (id) {
> + case KVM_REG_PPC_MAS0:
> + vcpu->arch.shared->mas0 =3D set_reg_val(id, *val);
> + break;
> + case KVM_REG_PPC_MAS1:
> + vcpu->arch.shared->mas1 =3D set_reg_val(id, *val);
> + break;
> + case KVM_REG_PPC_MAS2:
> + vcpu->arch.shared->mas2 =3D set_reg_val(id, *val);
> + break;
> + case KVM_REG_PPC_MAS7_3:
> + vcpu->arch.shared->mas7_3 =3D set_reg_val(id, *val);
> + break;
> + case KVM_REG_PPC_MAS4:
> + vcpu->arch.shared->mas4 =3D set_reg_val(id, *val);
> + break;
> + case KVM_REG_PPC_MAS6:
> + vcpu->arch.shared->mas6 =3D set_reg_val(id, *val);
> + break;
> + case KVM_REG_PPC_MMUCFG: {
> + u32 mmucfg =3D set_reg_val(id, *val);
> + vcpu->arch.mmucfg =3D mmucfg & ~MMUCFG_LPIDSIZE;
> + break;
> + }
Do we really want to allow arbitrary MMUCFG changes? It won't =20
magically make us able to support larger RAs, PIDs, different MAVN, etc.
> + case KVM_REG_PPC_TLB0CFG:
> + case KVM_REG_PPC_TLB1CFG:
> + case KVM_REG_PPC_TLB2CFG:
> + case KVM_REG_PPC_TLB3CFG: {
> + u32 tlbncfg =3D set_reg_val(id, =20
> *val); =09
> + u32 geometry_mask =3D TLBnCFG_N_ENTRY | TLBnCFG_ASSOC;
> + i =3D id - KVM_REG_PPC_TLB0CFG;
> +
> + /* MMU geometry (way/size) can be set only using SW_TLB =20
> */
> + if ((vcpu->arch.tlbcfg[i] & geometry_mask) !=3D
> + (tlbncfg & geometry_mask))
> + r =3D -EINVAL;
> +
> + vcpu->arch.tlbcfg[i] =3D set_reg_val(id, *val);
> + break;
> + }
Likewise -- just because QEMU sets a bit here doesn't mean KVM can =20
support it.
I thought the initial plan for setting these config registers was to =20
accept it if it exactly matches what KVM already has, and give an error =20
otherwise -- thus allowing for the possibliity of accepting certain =20
specific updates in the future.
-Scott=
next prev parent reply other threads:[~2013-03-19 17:26 UTC|newest]
Thread overview: 6+ messages / expand[flat|nested] mbox.gz Atom feed top
2013-03-19 17:17 [PATCH] KVM: PPC: e500: Expose MMU registers via ONE_REG Mihai Caraman
2013-03-19 17:26 ` Scott Wood [this message]
2013-03-21 10:06 ` Alexander Graf
2013-03-21 11:02 ` Caraman Mihai Claudiu-B02008
2013-03-21 11:06 ` Alexander Graf
2013-03-21 11:42 ` Caraman Mihai Claudiu-B02008
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