[PATCH 2/5] powerpc/fsl-booke: Add initial silicon device tree files for B4860 and B4420

[PATCH 2/5] powerpc/fsl-booke: Add initial silicon device tree files for B4860 and B4420

[Shaveta Leekha]

B4860 and B4420 are similar that share some commonalities

* common features have been added in b4si-pre.dtsi and b4si-post.dtsi
* differences are added in respective silicon files of B4860 and B4420

There are several things missing from the device trees of B4860 and B4420:

* DPAA related nodes (Qman, Bman, Fman, Rman)
* DSP related nodes/information

Signed-off-by: Shaveta Leekha <shaveta@freescale.com>
Signed-off-by: Zhao Chenhui <chenhui.zhao@freescale.com>
Signed-off-by: Li Yang <leoli@freescale.com>
Signed-off-by: Tang Yuantian <Yuantian.Tang@freescale.com>
Signed-off-by: Varun Sethi <Varun.Sethi@freescale.com>
Signed-off-by: Minghuan Lian <Minghuan.Lian@freescale.com>
Signed-off-by: Ramneek Mehresh <ramneek.mehresh@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
Signed-off-by: Andy Fleming <afleming@freescale.com>
Signed-off-by: Vakul Garg <vakul@freescale.com>
---
 arch/powerpc/boot/dts/fsl/b4420si-post.dtsi |   94 ++++++++++
 arch/powerpc/boot/dts/fsl/b4420si-pre.dtsi  |   49 +++++
 arch/powerpc/boot/dts/fsl/b4860si-post.dtsi |  138 ++++++++++++++
 arch/powerpc/boot/dts/fsl/b4860si-pre.dtsi  |   59 ++++++
 arch/powerpc/boot/dts/fsl/b4si-post.dtsi    |  262 +++++++++++++++++++++++++++
 arch/powerpc/boot/dts/fsl/b4si-pre.dtsi     |   65 +++++++
 6 files changed, 667 insertions(+), 0 deletions(-)
 create mode 100644 arch/powerpc/boot/dts/fsl/b4420si-post.dtsi
 create mode 100644 arch/powerpc/boot/dts/fsl/b4420si-pre.dtsi
 create mode 100644 arch/powerpc/boot/dts/fsl/b4860si-post.dtsi
 create mode 100644 arch/powerpc/boot/dts/fsl/b4860si-pre.dtsi
 create mode 100644 arch/powerpc/boot/dts/fsl/b4si-post.dtsi
 create mode 100644 arch/powerpc/boot/dts/fsl/b4si-pre.dtsi

diff --git a/arch/powerpc/boot/dts/fsl/b4420si-post.dtsi b/arch/powerpc/boot/dts/fsl/b4420si-post.dtsi
new file mode 100644
index 0000000..bba0c03
--- /dev/null
+++ b/arch/powerpc/boot/dts/fsl/b4420si-post.dtsi
@@ -0,0 +1,94 @@
+/*
+ * B4420 Silicon/SoC Device Tree Source (post include)
+ *
+ * Copyright 2012 Freescale Semiconductor, Inc.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *     * Redistributions of source code must retain the above copyright
+ *       notice, this list of conditions and the following disclaimer.
+ *     * Redistributions in binary form must reproduce the above copyright
+ *       notice, this list of conditions and the following disclaimer in the
+ *       documentation and/or other materials provided with the distribution.
+ *     * Neither the name of Freescale Semiconductor nor the
+ *       names of its contributors may be used to endorse or promote products
+ *       derived from this software without specific prior written permission.
+ *
+ *
+ * ALTERNATIVELY, this software may be distributed under the terms of the
+ * GNU General Public License ("GPL") as published by the Free Software
+ * Foundation, either version 2 of that License or (at your option) any
+ * later version.
+ *
+ * This software is provided by Freescale Semiconductor "as is" and any
+ * express or implied warranties, including, but not limited to, the implied
+ * warranties of merchantability and fitness for a particular purpose are
+ * disclaimed. In no event shall Freescale Semiconductor be liable for any
+ * direct, indirect, incidental, special, exemplary, or consequential damages
+ * (including, but not limited to, procurement of substitute goods or services;
+ * loss of use, data, or profits; or business interruption) however caused and
+ * on any theory of liability, whether in contract, strict liability, or tort
+ * (including negligence or otherwise) arising in any way out of the use of
+ * this software, even if advised of the possibility of such damage.
+ */
+
+/include/ "b4si-post.dtsi"
+
+/* controller at 0x200000 */
+&pci0 {
+	compatible = "fsl,b4420-pcie", "fsl,qoriq-pcie-v2.4";
+};
+
+&dcsr {
+	dcsr-epu@0 {
+		compatible = "fsl,b4420-dcsr-epu", "fsl,dcsr-epu";
+	};
+	dcsr-npc {
+		compatible = "fsl,b4420-dcsr-cnpc", "fsl,dcsr-cnpc";
+	};
+	dcsr-dpaa@9000 {
+		compatible = "fsl,b4420-dcsr-dpaa", "fsl,dcsr-dpaa";
+	};
+	dcsr-ocn@11000 {
+		compatible = "fsl,b4420-dcsr-ocn", "fsl,dcsr-ocn";
+	};
+	dcsr-nal@18000 {
+		compatible = "fsl,b4420-dcsr-nal", "fsl,dcsr-nal";
+	};
+	dcsr-rcpm@22000 {
+		compatible = "fsl,b4420-dcsr-rcpm", "fsl,dcsr-rcpm";
+	};
+	dcsr-snpc@30000 {
+		compatible = "fsl,b4420-dcsr-snpc", "fsl,dcsr-snpc";
+	};
+	dcsr-snpc@31000 {
+		compatible = "fsl,b4420-dcsr-snpc", "fsl,dcsr-snpc";
+	};
+	dcsr-cpu-sb-proxy@108000 {
+		compatible = "fsl,dcsr-e6500-sb-proxy", "fsl,dcsr-cpu-sb-proxy";
+		cpu-handle = <&cpu1>;
+		reg = <0x108000 0x1000 0x109000 0x1000>;
+	};
+};
+
+&soc {
+	cpc: l3-cache-controller@10000 {
+		compatible = "fsl,b4420-l3-cache-controller", "cache";
+	};
+
+	corenet-cf@18000 {
+		compatible = "fsl,b4420-corenet-cf";
+	};
+
+	guts: global-utilities@e0000 {
+		compatible = "fsl,b4420-device-config", "fsl,qoriq-device-config-2.0";
+	};
+
+	clockgen: global-utilities@e1000 {
+		compatible = "fsl,b4420-clockgen", "fsl,qoriq-clockgen-2";
+	};
+
+	L2: l2-cache-controller@c20000 {
+		compatible = "fsl,b4420-l2-cache-controller";
+	};
+};
diff --git a/arch/powerpc/boot/dts/fsl/b4420si-pre.dtsi b/arch/powerpc/boot/dts/fsl/b4420si-pre.dtsi
new file mode 100644
index 0000000..555b0e4
--- /dev/null
+++ b/arch/powerpc/boot/dts/fsl/b4420si-pre.dtsi
@@ -0,0 +1,49 @@
+/*
+ * B4420 Silicon/SoC Device Tree Source (pre include)
+ *
+ * Copyright 2012 Freescale Semiconductor, Inc.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *     * Redistributions of source code must retain the above copyright
+ *       notice, this list of conditions and the following disclaimer.
+ *     * Redistributions in binary form must reproduce the above copyright
+ *       notice, this list of conditions and the following disclaimer in the
+ *       documentation and/or other materials provided with the distribution.
+ *     * Neither the name of Freescale Semiconductor nor the
+ *       names of its contributors may be used to endorse or promote products
+ *       derived from this software without specific prior written permission.
+ *
+ *
+ * ALTERNATIVELY, this software may be distributed under the terms of the
+ * GNU General Public License ("GPL") as published by the Free Software
+ * Foundation, either version 2 of that License or (at your option) any
+ * later version.
+ *
+ * This software is provided by Freescale Semiconductor "as is" and any
+ * express or implied warranties, including, but not limited to, the implied
+ * warranties of merchantability and fitness for a particular purpose are
+ * disclaimed. In no event shall Freescale Semiconductor be liable for any
+ * direct, indirect, incidental, special, exemplary, or consequential damages
+ * (including, but not limited to, procurement of substitute goods or services;
+ * loss of use, data, or profits; or business interruption) however caused and
+ * on any theory of liability, whether in contract, strict liability, or tort
+ * (including negligence or otherwise) arising in any way out of the use of
+ * this software, even if advised of the possibility of such damage.
+ */
+
+/dts-v1/;
+
+/include/ "b4si-pre.dtsi"
+
+/ {
+	compatible = "fsl,B4420";
+
+	cpus {
+		cpu1: PowerPC,e6500@1 {
+			device_type = "cpu";
+			reg = <2 3>;
+			next-level-cache = <&L2>;
+		};
+	};
+};
diff --git a/arch/powerpc/boot/dts/fsl/b4860si-post.dtsi b/arch/powerpc/boot/dts/fsl/b4860si-post.dtsi
new file mode 100644
index 0000000..f43910f
--- /dev/null
+++ b/arch/powerpc/boot/dts/fsl/b4860si-post.dtsi
@@ -0,0 +1,138 @@
+/*
+ * B4860 Silicon/SoC Device Tree Source (post include)
+ *
+ * Copyright 2012 Freescale Semiconductor Inc.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *     * Redistributions of source code must retain the above copyright
+ *       notice, this list of conditions and the following disclaimer.
+ *     * Redistributions in binary form must reproduce the above copyright
+ *       notice, this list of conditions and the following disclaimer in the
+ *       documentation and/or other materials provided with the distribution.
+ *     * Neither the name of Freescale Semiconductor nor the
+ *       names of its contributors may be used to endorse or promote products
+ *       derived from this software without specific prior written permission.
+ *
+ *
+ * ALTERNATIVELY, this software may be distributed under the terms of the
+ * GNU General Public License ("GPL") as published by the Free Software
+ * Foundation, either version 2 of that License or (at your option) any
+ * later version.
+ *
+ * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY
+ * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+/include/ "b4si-post.dtsi"
+
+/* controller at 0x200000 */
+&pci0 {
+	compatible = "fsl,b4860-pcie", "fsl,qoriq-pcie-v2.4";
+};
+
+&rio {
+	compatible = "fsl,srio";
+	interrupts = <16 2 1 11>;
+	#address-cells = <2>;
+	#size-cells = <2>;
+	fsl,iommu-parent = <&pamu0>;
+	ranges;
+
+	port1 {
+		#address-cells = <2>;
+		#size-cells = <2>;
+		cell-index = <1>;
+		fsl,liodn-reg = <&guts 0x510>; /* RIO1LIODNR */
+	};
+
+	port2 {
+		#address-cells = <2>;
+		#size-cells = <2>;
+		cell-index = <2>;
+		fsl,liodn-reg = <&guts 0x514>; /* RIO2LIODNR */
+	};
+};
+
+&dcsr {
+	dcsr-epu@0 {
+		compatible = "fsl,b4860-dcsr-epu", "fsl,dcsr-epu";
+	};
+	dcsr-npc {
+		compatible = "fsl,b4860-dcsr-cnpc", "fsl,dcsr-cnpc";
+	};
+	dcsr-dpaa@9000 {
+		compatible = "fsl,b4860-dcsr-dpaa", "fsl,dcsr-dpaa";
+	};
+	dcsr-ocn@11000 {
+		compatible = "fsl,b4860-dcsr-ocn", "fsl,dcsr-ocn";
+	};
+	dcsr-ddr@13000 {
+		compatible = "fsl,dcsr-ddr";
+		dev-handle = <&ddr2>;
+		reg = <0x13000 0x1000>;
+	};
+	dcsr-nal@18000 {
+		compatible = "fsl,b4860-dcsr-nal", "fsl,dcsr-nal";
+	};
+	dcsr-rcpm@22000 {
+		compatible = "fsl,b4860-dcsr-rcpm", "fsl,dcsr-rcpm";
+	};
+	dcsr-snpc@30000 {
+		compatible = "fsl,b4860-dcsr-snpc", "fsl,dcsr-snpc";
+	};
+	dcsr-snpc@31000 {
+		compatible = "fsl,b4860-dcsr-snpc", "fsl,dcsr-snpc";
+	};
+	dcsr-cpu-sb-proxy@108000 {
+		compatible = "fsl,dcsr-e6500-sb-proxy", "fsl,dcsr-cpu-sb-proxy";
+		cpu-handle = <&cpu1>;
+		reg = <0x108000 0x1000 0x109000 0x1000>;
+	};
+	dcsr-cpu-sb-proxy@110000 {
+		compatible = "fsl,dcsr-e6500-sb-proxy", "fsl,dcsr-cpu-sb-proxy";
+		cpu-handle = <&cpu2>;
+		reg = <0x110000 0x1000 0x111000 0x1000>;
+	};
+	dcsr-cpu-sb-proxy@118000 {
+		compatible = "fsl,dcsr-e6500-sb-proxy", "fsl,dcsr-cpu-sb-proxy";
+		cpu-handle = <&cpu3>;
+		reg = <0x118000 0x1000 0x119000 0x1000>;
+	};
+};
+
+&soc {
+	ddr2: memory-controller@9000 {
+		compatible = "fsl,qoriq-memory-controller-v4.5", "fsl,qoriq-memory-controller";
+		reg = <0x9000 0x1000>;
+		interrupts = <16 2 1 9>;
+	};
+
+	cpc: l3-cache-controller@10000 {
+		compatible = "fsl,b4860-l3-cache-controller", "cache";
+	};
+
+	corenet-cf@18000 {
+		compatible = "fsl,b4860-corenet-cf";
+	};
+
+	guts: global-utilities@e0000 {
+		compatible = "fsl,b4860-device-config", "fsl,qoriq-device-config-2.0";
+	};
+
+	clockgen: global-utilities@e1000 {
+		compatible = "fsl,b4860-clockgen", "fsl,qoriq-clockgen-2";
+	};
+
+	L2: l2-cache-controller@c20000 {
+		compatible = "fsl,b4860-l2-cache-controller";
+	};
+};
diff --git a/arch/powerpc/boot/dts/fsl/b4860si-pre.dtsi b/arch/powerpc/boot/dts/fsl/b4860si-pre.dtsi
new file mode 100644
index 0000000..f5737a0
--- /dev/null
+++ b/arch/powerpc/boot/dts/fsl/b4860si-pre.dtsi
@@ -0,0 +1,59 @@
+/*
+ * B4860 Silicon/SoC Device Tree Source (pre include)
+ *
+ * Copyright 2012 Freescale Semiconductor Inc.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *     * Redistributions of source code must retain the above copyright
+ *       notice, this list of conditions and the following disclaimer.
+ *     * Redistributions in binary form must reproduce the above copyright
+ *       notice, this list of conditions and the following disclaimer in the
+ *       documentation and/or other materials provided with the distribution.
+ *     * Neither the name of Freescale Semiconductor nor the
+ *       names of its contributors may be used to endorse or promote products
+ *       derived from this software without specific prior written permission.
+ *
+ *
+ * ALTERNATIVELY, this software may be distributed under the terms of the
+ * GNU General Public License ("GPL") as published by the Free Software
+ * Foundation, either version 2 of that License or (at your option) any
+ * later version.
+ *
+ * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY
+ * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+/dts-v1/;
+
+/include/ "b4si-pre.dtsi"
+
+/ {
+	compatible = "fsl,B4860";
+
+	cpus {
+		cpu1: PowerPC,e6500@1 {
+			device_type = "cpu";
+			reg = <2 3>;
+			next-level-cache = <&L2>;
+		};
+		cpu2: PowerPC,e6500@2 {
+			device_type = "cpu";
+			reg = <4 5>;
+			next-level-cache = <&L2>;
+		};
+		cpu3: PowerPC,e6500@3 {
+			device_type = "cpu";
+			reg = <6 7>;
+			next-level-cache = <&L2>;
+		};
+	};
+};
diff --git a/arch/powerpc/boot/dts/fsl/b4si-post.dtsi b/arch/powerpc/boot/dts/fsl/b4si-post.dtsi
new file mode 100644
index 0000000..06c97a2
--- /dev/null
+++ b/arch/powerpc/boot/dts/fsl/b4si-post.dtsi
@@ -0,0 +1,262 @@
+/*
+ * B4420 Silicon/SoC Device Tree Source (post include)
+ *
+ * Copyright 2012 Freescale Semiconductor, Inc.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *     * Redistributions of source code must retain the above copyright
+ *       notice, this list of conditions and the following disclaimer.
+ *     * Redistributions in binary form must reproduce the above copyright
+ *       notice, this list of conditions and the following disclaimer in the
+ *       documentation and/or other materials provided with the distribution.
+ *     * Neither the name of Freescale Semiconductor nor the
+ *       names of its contributors may be used to endorse or promote products
+ *       derived from this software without specific prior written permission.
+ *
+ *
+ * ALTERNATIVELY, this software may be distributed under the terms of the
+ * GNU General Public License ("GPL") as published by the Free Software
+ * Foundation, either version 2 of that License or (at your option) any
+ * later version.
+ *
+ * This software is provided by Freescale Semiconductor "as is" and any
+ * express or implied warranties, including, but not limited to, the implied
+ * warranties of merchantability and fitness for a particular purpose are
+ * disclaimed. In no event shall Freescale Semiconductor be liable for any
+ * direct, indirect, incidental, special, exemplary, or consequential damages
+ * (including, but not limited to, procurement of substitute goods or services;
+ * loss of use, data, or profits; or business interruption) however caused and
+ * on any theory of liability, whether in contract, strict liability, or tort
+ * (including negligence or otherwise) arising in any way out of the use of
+ * this software, even if advised of the possibility of such damage.
+ */
+
+&ifc {
+	#address-cells = <2>;
+	#size-cells = <1>;
+	compatible = "fsl,ifc", "simple-bus";
+	interrupts = <25 2 0 0>;
+};
+
+/* controller at 0x200000 */
+&pci0 {
+	compatible = "fsl,b4-pcie", "fsl,qoriq-pcie-v2.4";
+	device_type = "pci";
+	#size-cells = <2>;
+	#address-cells = <3>;
+	bus-range = <0x0 0xff>;
+	interrupts = <20 2 0 0>;
+	fsl,iommu-parent = <&pamu0>;
+	pcie@0 {
+		#interrupt-cells = <1>;
+		#size-cells = <2>;
+		#address-cells = <3>;
+		device_type = "pci";
+		interrupts = <20 2 0 0>;
+		interrupt-map-mask = <0xf800 0 0 7>;
+		interrupt-map = <
+			/* IDSEL 0x0 */
+			0000 0 0 1 &mpic 40 1 0 0
+			0000 0 0 2 &mpic 1 1 0 0
+			0000 0 0 3 &mpic 2 1 0 0
+			0000 0 0 4 &mpic 3 1 0 0
+			>;
+	};
+};
+
+&dcsr {
+	#address-cells = <1>;
+	#size-cells = <1>;
+	compatible = "fsl,dcsr", "simple-bus";
+
+	dcsr-epu@0 {
+		compatible = "fsl,b4-dcsr-epu", "fsl,dcsr-epu";
+		interrupts = <52 2 0 0
+			      84 2 0 0
+			      85 2 0 0
+			      94 2 0 0
+			      95 2 0 0>;
+		reg = <0x0 0x1000>;
+	};
+	dcsr-npc {
+		compatible = "fsl,b4-dcsr-cnpc", "fsl,dcsr-cnpc";
+		reg = <0x1000 0x1000 0x1002000 0x10000>;
+	};
+	dcsr-nxc@2000 {
+		compatible = "fsl,dcsr-nxc";
+		reg = <0x2000 0x1000>;
+	};
+	dcsr-corenet {
+		compatible = "fsl,dcsr-corenet";
+		reg = <0x8000 0x1000 0x1A000 0x1000>;
+	};
+	dcsr-dpaa@9000 {
+		compatible = "fsl,b4-dcsr-dpaa", "fsl,dcsr-dpaa";
+		reg = <0x9000 0x1000>;
+	};
+	dcsr-ocn@11000 {
+		compatible = "fsl,b4-dcsr-ocn", "fsl,dcsr-ocn";
+		reg = <0x11000 0x1000>;
+	};
+	dcsr-ddr@12000 {
+		compatible = "fsl,dcsr-ddr";
+		dev-handle = <&ddr1>;
+		reg = <0x12000 0x1000>;
+	};
+	dcsr-nal@18000 {
+		compatible = "fsl,b4-dcsr-nal", "fsl,dcsr-nal";
+		reg = <0x18000 0x1000>;
+	};
+	dcsr-rcpm@22000 {
+		compatible = "fsl,b4-dcsr-rcpm", "fsl,dcsr-rcpm";
+		reg = <0x22000 0x1000>;
+	};
+	dcsr-snpc@30000 {
+		compatible = "fsl,b4-dcsr-snpc", "fsl,dcsr-snpc";
+		reg = <0x30000 0x1000 0x1022000 0x10000>;
+	};
+	dcsr-snpc@31000 {
+		compatible = "fsl,b4-dcsr-snpc", "fsl,dcsr-snpc";
+		reg = <0x31000 0x1000 0x1042000 0x10000>;
+	};
+	dcsr-cpu-sb-proxy@100000 {
+		compatible = "fsl,dcsr-e6500-sb-proxy", "fsl,dcsr-cpu-sb-proxy";
+		cpu-handle = <&cpu0>;
+		reg = <0x100000 0x1000 0x101000 0x1000>;
+	};
+};
+
+&soc {
+	#address-cells = <1>;
+	#size-cells = <1>;
+	device_type = "soc";
+	compatible = "simple-bus";
+
+	soc-sram-error {
+		compatible = "fsl,soc-sram-error";
+		interrupts = <16 2 1 2>;
+	};
+
+	corenet-law@0 {
+		compatible = "fsl,corenet-law";
+		reg = <0x0 0x1000>;
+		fsl,num-laws = <32>;
+	};
+
+	ddr1: memory-controller@8000 {
+		compatible = "fsl,qoriq-memory-controller-v4.5", "fsl,qoriq-memory-controller";
+		reg = <0x8000 0x1000>;
+		interrupts = <16 2 1 8>;
+	};
+
+	cpc: l3-cache-controller@10000 {
+		compatible = "fsl,b4-l3-cache-controller", "cache";
+		reg = <0x10000 0x1000>;
+		interrupts = <16 2 1 4>;
+	};
+
+	corenet-cf@18000 {
+		compatible = "fsl,b4-corenet-cf";
+		reg = <0x18000 0x1000>;
+		interrupts = <16 2 1 0>;
+		fsl,ccf-num-csdids = <32>;
+		fsl,ccf-num-snoopids = <32>;
+	};
+
+	iommu@20000 {
+		compatible =  "fsl,pamu-v1.0", "fsl,pamu";
+		reg = <0x20000 0x4000>;
+		#address-cells = <1>;
+		#size-cells = <1>;
+		interrupts = <
+			24 2 0 0
+			16 2 1 1>;
+
+
+		/* PCIe, DMA, SRIO */
+		pamu0: pamu@0 {
+			reg = <0 0x1000>;
+			fsl,primary-cache-geometry = <8 1>;
+			fsl,secondary-cache-geometry = <32 2>;
+		};
+
+		/* AXI2, Maple */
+		pamu1: pamu@1000 {
+			reg = <0x1000 0x1000>;
+			fsl,primary-cache-geometry = <32 1>;
+			fsl,secondary-cache-geometry = <32 2>;
+		};
+
+		/* Q/BMan */
+		pamu2: pamu@2000 {
+			reg = <0x2000 0x1000>;
+			fsl,primary-cache-geometry = <32 1>;
+			fsl,secondary-cache-geometry = <32 2>;
+		};
+
+		/* AXI1, FMAN */
+		pamu3: pamu@3000 {
+			reg = <0x3000 0x1000>;
+			fsl,primary-cache-geometry = <32 1>;
+			fsl,secondary-cache-geometry = <32 2>;
+		};
+	};
+
+/include/ "qoriq-mpic.dtsi"
+
+	guts: global-utilities@e0000 {
+		compatible = "fsl,b4-device-config";
+		reg = <0xe0000 0xe00>;
+		fsl,has-rstcr;
+		fsl,liodn-bits = <12>;
+	};
+
+	rcpm: global-utilities@e2000 {
+		compatible = "fsl,b4-rcpm", "fsl,qoriq-rcpm-2";
+		reg = <0xe2000 0x1000>;
+	};
+
+/include/ "qoriq-dma-0.dtsi"
+	dma@100300 {
+		fsl,iommu-parent = <&pamu0>;
+		fsl,liodn-reg = <&guts 0x580>; /* DMA1LIODNR */
+	};
+
+/include/ "qoriq-dma-1.dtsi"
+	dma@101300 {
+		fsl,iommu-parent = <&pamu0>;
+		fsl,liodn-reg = <&guts 0x584>; /* DMA2LIODNR */
+	};
+
+/include/ "qonverge-usb2-dr-0.dtsi"
+	usb0: usb@210000 {
+		compatible = "fsl-usb2-dr-v2.4", "fsl-usb2-dr";
+		fsl,iommu-parent = <&pamu1>;
+		fsl,liodn-reg = <&guts 0x520>; /* USB1LIODNR */
+	};
+
+/include/ "qoriq-espi-0.dtsi"
+	spi@110000 {
+		fsl,espi-num-chipselects = <4>;
+	};
+
+/include/ "qoriq-esdhc-0.dtsi"
+	sdhc@114000 {
+		sdhci,auto-cmd12;
+		fsl,iommu-parent = <&pamu1>;
+		fsl,liodn-reg = <&guts 0x530>; /* eSDHCLIODNR */
+	};
+
+/include/ "qoriq-i2c-0.dtsi"
+/include/ "qoriq-i2c-1.dtsi"
+/include/ "qoriq-duart-0.dtsi"
+/include/ "qoriq-duart-1.dtsi"
+/include/ "qoriq-sec5.3-0.dtsi"
+
+	L2: l2-cache-controller@c20000 {
+		compatible = "fsl,b4-l2-cache-controller";
+                reg = <0xc20000 0x1000>;
+		next-level-cache = <&cpc>;
+	};
+};
diff --git a/arch/powerpc/boot/dts/fsl/b4si-pre.dtsi b/arch/powerpc/boot/dts/fsl/b4si-pre.dtsi
new file mode 100644
index 0000000..b6161c8
--- /dev/null
+++ b/arch/powerpc/boot/dts/fsl/b4si-pre.dtsi
@@ -0,0 +1,65 @@
+/*
+ * B4420 Silicon/SoC Device Tree Source (pre include)
+ *
+ * Copyright 2012 Freescale Semiconductor, Inc.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *     * Redistributions of source code must retain the above copyright
+ *       notice, this list of conditions and the following disclaimer.
+ *     * Redistributions in binary form must reproduce the above copyright
+ *       notice, this list of conditions and the following disclaimer in the
+ *       documentation and/or other materials provided with the distribution.
+ *     * Neither the name of Freescale Semiconductor nor the
+ *       names of its contributors may be used to endorse or promote products
+ *       derived from this software without specific prior written permission.
+ *
+ *
+ * ALTERNATIVELY, this software may be distributed under the terms of the
+ * GNU General Public License ("GPL") as published by the Free Software
+ * Foundation, either version 2 of that License or (at your option) any
+ * later version.
+ *
+ * This software is provided by Freescale Semiconductor "as is" and any
+ * express or implied warranties, including, but not limited to, the implied
+ * warranties of merchantability and fitness for a particular purpose are
+ * disclaimed. In no event shall Freescale Semiconductor be liable for any
+ * direct, indirect, incidental, special, exemplary, or consequential damages
+ * (including, but not limited to, procurement of substitute goods or services;
+ * loss of use, data, or profits; or business interruption) however caused and
+ * on any theory of liability, whether in contract, strict liability, or tort
+ * (including negligence or otherwise) arising in any way out of the use of
+ * this software, even if advised of the possibility of such damage.
+ */
+
+/ {
+	compatible = "fsl,B4";
+	#address-cells = <2>;
+	#size-cells = <2>;
+	interrupt-parent = <&mpic>;
+
+	aliases {
+		ccsr = &soc;
+		dcsr = &dcsr;
+
+		serial0 = &serial0;
+		serial1 = &serial1;
+		serial2 = &serial2;
+		serial3 = &serial3;
+		pci0 = &pci0;
+		dma0 = &dma0;
+		dma1 = &dma1;
+		sdhc = &sdhc;
+	};
+
+	cpus {
+		#address-cells = <1>;
+		#size-cells = <0>;
+
+		cpu0: PowerPC,e6500@0 {
+			device_type = "cpu";
+			reg = <0 1>;
+			next-level-cache = <&L2>;
+		};
+	};
+};
-- 
1.7.6.GIT

[PATCH 3/5] powerpc/fsl-booke: Add initial B4860QDS and B4420QDS board device tree

[Shaveta Leekha]

B4860QDS and B4420QDS share same QDS board

* common board features have been added in b4qds.dts
* various board differences are in respective files of B4860 and B4420

Signed-off-by: Shaveta Leekha <shaveta@freescale.com>
Signed-off-by: Minghuan Lian <Minghuan.Lian@freescale.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>
Signed-off-by: Poonam Aggrwal <poonam.aggrwal@freescale.com>
Signed-off-by: Ramneek Mehresh <ramneek.mehresh@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
---
 arch/powerpc/boot/dts/b4420qds.dts |   50 +++++++++++
 arch/powerpc/boot/dts/b4860qds.dts |   61 +++++++++++++
 arch/powerpc/boot/dts/b4qds.dts    |  171 ++++++++++++++++++++++++++++++++++++
 3 files changed, 282 insertions(+), 0 deletions(-)
 create mode 100644 arch/powerpc/boot/dts/b4420qds.dts
 create mode 100644 arch/powerpc/boot/dts/b4860qds.dts
 create mode 100644 arch/powerpc/boot/dts/b4qds.dts

diff --git a/arch/powerpc/boot/dts/b4420qds.dts b/arch/powerpc/boot/dts/b4420qds.dts
new file mode 100644
index 0000000..923156d
--- /dev/null
+++ b/arch/powerpc/boot/dts/b4420qds.dts
@@ -0,0 +1,50 @@
+/*
+ * B4420DS Device Tree Source
+ *
+ * Copyright 2012 Freescale Semiconductor, Inc.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *     * Redistributions of source code must retain the above copyright
+ *       notice, this list of conditions and the following disclaimer.
+ *     * Redistributions in binary form must reproduce the above copyright
+ *       notice, this list of conditions and the following disclaimer in the
+ *       documentation and/or other materials provided with the distribution.
+ *     * Neither the name of Freescale Semiconductor nor the
+ *       names of its contributors may be used to endorse or promote products
+ *       derived from this software without specific prior written permission.
+ *
+ *
+ * ALTERNATIVELY, this software may be distributed under the terms of the
+ * GNU General Public License ("GPL") as published by the Free Software
+ * Foundation, either version 2 of that License or (at your option) any
+ * later version.
+ *
+ * This software is provided by Freescale Semiconductor "as is" and any
+ * express or implied warranties, including, but not limited to, the implied
+ * warranties of merchantability and fitness for a particular purpose are
+ * disclaimed. In no event shall Freescale Semiconductor be liable for any
+ * direct, indirect, incidental, special, exemplary, or consequential damages
+ * (including, but not limited to, procurement of substitute goods or services;
+ * loss of use, data, or profits; or business interruption) however caused and
+ * on any theory of liability, whether in contract, strict liability, or tort
+ * (including negligence or otherwise) arising in any way out of the use of
+ * this software, even if advised of the possibility of such damage.
+ */
+
+/include/ "fsl/b4420si-pre.dtsi"
+/include/ "b4qds.dts"
+
+/ {
+	model = "fsl,B4420QDS";
+	compatible = "fsl,B4420QDS";
+
+	ifc: localbus@ffe124000 {
+		board-control@3,0 {
+			compatible = "fsl,b4420qds-fpga", "fsl,fpga-qixis";
+		};
+	};
+
+};
+
+/include/ "fsl/b4420si-post.dtsi"
diff --git a/arch/powerpc/boot/dts/b4860qds.dts b/arch/powerpc/boot/dts/b4860qds.dts
new file mode 100644
index 0000000..78907f3
--- /dev/null
+++ b/arch/powerpc/boot/dts/b4860qds.dts
@@ -0,0 +1,61 @@
+/*
+ * B4860DS Device Tree Source
+ *
+ * Copyright 2012 Freescale Semiconductor Inc.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *     * Redistributions of source code must retain the above copyright
+ *       notice, this list of conditions and the following disclaimer.
+ *     * Redistributions in binary form must reproduce the above copyright
+ *       notice, this list of conditions and the following disclaimer in the
+ *       documentation and/or other materials provided with the distribution.
+ *     * Neither the name of Freescale Semiconductor nor the
+ *       names of its contributors may be used to endorse or promote products
+ *       derived from this software without specific prior written permission.
+ *
+ *
+ * ALTERNATIVELY, this software may be distributed under the terms of the
+ * GNU General Public License ("GPL") as published by the Free Software
+ * Foundation, either version 2 of that License or (at your option) any
+ * later version.
+ *
+ * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY
+ * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+/include/ "fsl/b4860si-pre.dtsi"
+/include/ "b4qds.dts"
+
+/ {
+	model = "fsl,B4860QDS";
+	compatible = "fsl,B4860QDS";
+
+	ifc: localbus@ffe124000 {
+		board-control@3,0 {
+			compatible = "fsl,b4860qds-fpga", "fsl,fpga-qixis";
+		};
+	};
+
+	rio: rapidio@ffe0c0000 {
+		reg = <0xf 0xfe0c0000 0 0x11000>;
+
+		port1 {
+			ranges = <0 0 0xc 0x20000000 0 0x10000000>;
+		};
+		port2 {
+			ranges = <0 0 0xc 0x30000000 0 0x10000000>;
+		};
+	};
+
+};
+
+/include/ "fsl/b4860si-post.dtsi"
diff --git a/arch/powerpc/boot/dts/b4qds.dts b/arch/powerpc/boot/dts/b4qds.dts
new file mode 100644
index 0000000..f99aa3e
--- /dev/null
+++ b/arch/powerpc/boot/dts/b4qds.dts
@@ -0,0 +1,171 @@
+/*
+ * B4420DS Device Tree Source
+ *
+ * Copyright 2012 Freescale Semiconductor, Inc.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *     * Redistributions of source code must retain the above copyright
+ *       notice, this list of conditions and the following disclaimer.
+ *     * Redistributions in binary form must reproduce the above copyright
+ *       notice, this list of conditions and the following disclaimer in the
+ *       documentation and/or other materials provided with the distribution.
+ *     * Neither the name of Freescale Semiconductor nor the
+ *       names of its contributors may be used to endorse or promote products
+ *       derived from this software without specific prior written permission.
+ *
+ *
+ * ALTERNATIVELY, this software may be distributed under the terms of the
+ * GNU General Public License ("GPL") as published by the Free Software
+ * Foundation, either version 2 of that License or (at your option) any
+ * later version.
+ *
+ * This software is provided by Freescale Semiconductor "as is" and any
+ * express or implied warranties, including, but not limited to, the implied
+ * warranties of merchantability and fitness for a particular purpose are
+ * disclaimed. In no event shall Freescale Semiconductor be liable for any
+ * direct, indirect, incidental, special, exemplary, or consequential damages
+ * (including, but not limited to, procurement of substitute goods or services;
+ * loss of use, data, or profits; or business interruption) however caused and
+ * on any theory of liability, whether in contract, strict liability, or tort
+ * (including negligence or otherwise) arising in any way out of the use of
+ * this software, even if advised of the possibility of such damage.
+ */
+
+/include/ "fsl/b4si-pre.dtsi"
+
+/ {
+	model = "fsl,B4QDS";
+	compatible = "fsl,B4QDS";
+	#address-cells = <2>;
+	#size-cells = <2>;
+	interrupt-parent = <&mpic>;
+
+	ifc: localbus@ffe124000 {
+		reg = <0xf 0xfe124000 0 0x2000>;
+		ranges = <0 0 0xf 0xe8000000 0x08000000
+			  2 0 0xf 0xff800000 0x00010000
+			  3 0 0xf 0xffdf0000 0x00008000>;
+
+		nor@0,0 {
+			#address-cells = <1>;
+			#size-cells = <1>;
+			compatible = "cfi-flash";
+			reg = <0x0 0x0 0x8000000>;
+			bank-width = <2>;
+			device-width = <1>;
+		};
+
+		nand@2,0 {
+			#address-cells = <1>;
+			#size-cells = <1>;
+			compatible = "fsl,ifc-nand";
+			reg = <0x2 0x0 0x10000>;
+
+			partition@0 {
+				/* This location must not be altered  */
+				/* 1MB for u-boot Bootloader Image */
+				reg = <0x0 0x00100000>;
+				label = "NAND U-Boot Image";
+				read-only;
+			};
+
+			partition@100000 {
+				/* 1MB for DTB Image */
+				reg = <0x00100000 0x00100000>;
+				label = "NAND DTB Image";
+			};
+
+			partition@200000 {
+				/* 10MB for Linux Kernel Image */
+				reg = <0x00200000 0x00A00000>;
+				label = "NAND Linux Kernel Image";
+			};
+
+			partition@c00000 {
+				/* 500MB for Root file System Image */
+				reg = <0x00c00000 0x1F400000>;
+				label = "NAND RFS Image";
+			};
+		};
+
+		board-control@3,0 {
+			compatible = "fsl,b4qds-fpga", "fsl,fpga-qixis";
+			reg = <3 0 0x300>;
+		};
+	};
+
+	memory {
+		device_type = "memory";
+	};
+
+	dcsr: dcsr@f00000000 {
+		ranges = <0x00000000 0xf 0x00000000 0x01052000>;
+	};
+
+	soc: soc@ffe000000 {
+		ranges = <0x00000000 0xf 0xfe000000 0x1000000>;
+		reg = <0xf 0xfe000000 0 0x00001000>;
+		spi@110000 {
+			flash@0 {
+				#address-cells = <1>;
+				#size-cells = <1>;
+				compatible = "sst,sst25wf040";
+				reg = <0>;
+				spi-max-frequency = <40000000>; /* input clock */
+			};
+		};
+
+		sdhc@114000 {
+			/*Disabled as there is no sdhc connector on B4420QDS board*/
+			status = "disabled";
+		};
+
+		i2c@118000 {
+			eeprom@50 {
+				compatible = "at24,24c64";
+				reg = <0x50>;
+			};
+			eeprom@51 {
+				compatible = "at24,24c256";
+				reg = <0x51>;
+			};
+			eeprom@53 {
+				compatible = "at24,24c256";
+				reg = <0x53>;
+			};
+			eeprom@57 {
+				compatible = "at24,24c256";
+				reg = <0x57>;
+			};
+			rtc@68 {
+				compatible = "dallas,ds3232";
+				reg = <0x68>;
+			};
+		};
+
+		usb@210000 {
+			dr_mode = "host";
+			phy_type = "ulpi";
+		};
+
+	};
+
+	pci0: pcie@ffe200000 {
+		reg = <0xf 0xfe200000 0 0x10000>;
+		ranges = <0x02000000 0 0xe0000000 0xc 0x00000000 0x0 0x20000000
+			  0x01000000 0 0x00000000 0xf 0xf8000000 0x0 0x00010000>;
+		pcie@0 {
+			ranges = <0x02000000 0 0xe0000000
+				  0x02000000 0 0xe0000000
+				  0 0x20000000
+
+				  0x01000000 0 0x00000000
+				  0x01000000 0 0x00000000
+				  0 0x00010000>;
+		};
+	};
+
+};
+
+/include/ "fsl/b4si-post.dtsi"
-- 
1.7.6.GIT

[PATCH 4/5] powerpc/fsl-booke: Add B4_QDS board support

[Shaveta Leekha]

- Add support for B4 board in board file b4_qds.c,
  It is common for B4860, B4420 and B4220QDS as they share same QDS board
- Add B4QDS support in Kconfig and Makefile

B4860QDS is a high-performance computing evaluation, development and
test platform supporting the B4860 QorIQ Power Architecture processor,
with following major features:

    - Four dual-threaded e6500 Power Architecture processors
      organized in one cluster-each core runs up to 1.8 GHz
    - Two DDR3/3L controllers for high-speed memory interface each
      runs at up to 1866.67 MHz
    - CoreNet fabric that fully supports coherency using MESI protocol
      between the e6500 cores, SC3900 FVP cores, memories and
      external interfaces.
    - Data Path Acceleration Architecture having FMAN, QMan, BMan, SEC 5.3 and RMAN
    - Large internal cache memory with snooping and stashing capabilities
    - Sixteen 10-GHz SerDes lanes that serve:
        - Two SRIO interfaces. Each supports up to 4 lanes and
          a total of up to 8 lanes
        - Up to 8-lanes Common Public Radio Interface (CPRI) controller
          for glue-less antenna connection
        - Two 10-Gbit Ethernet controllers (10GEC)
        - Six 1G/2.5-Gbit Ethernet controllers for network communications
        - PCI Express controller
        - Debug (Aurora)
    - Various system peripherals

B4420 and B4220 have some differences in comparison to B4860 with fewer core/clusters(both SC3900 and e6500),
fewer DDR controllers, fewer serdes lanes, fewer SGMII interfaces and reduced target frequencies.

Key differences between B4860 and B4420:
B4420 has:
    - Fewer e6500 cores:
        1 cluster with 2 e6500 cores
    - Fewer SC3900 cores/clusters:
        1 cluster with 2 SC3900 cores per cluster
    - Single DDRC @ 1.6GHz
    - 2 X 4 lane serdes
    - 3 SGMII interfaces
    - no sRIO
    - no 10G

Key differences between B4860 and B4220:
B4220 has:
    - Fewer e6500 cores:
        1 cluster with 1 e6500 core
    - Fewer SC3900 cores/clusters:
        1 cluster with 2 SC3900 cores per cluster
    - Single DDRC @ 1.33GHz
    - 2 X 2 lane serdes
    - 2 SGMII interfaces
    - no sRIO
    - no 10G

Signed-off-by: Shaveta Leekha <shaveta@freescale.com>
---
 arch/powerpc/platforms/85xx/Kconfig  |   17 ++++++
 arch/powerpc/platforms/85xx/Makefile |    1 +
 arch/powerpc/platforms/85xx/b4_qds.c |  102 ++++++++++++++++++++++++++++++++++
 3 files changed, 120 insertions(+), 0 deletions(-)
 create mode 100644 arch/powerpc/platforms/85xx/b4_qds.c

diff --git a/arch/powerpc/platforms/85xx/Kconfig b/arch/powerpc/platforms/85xx/Kconfig
index 31dc066..8f02b05 100644
--- a/arch/powerpc/platforms/85xx/Kconfig
+++ b/arch/powerpc/platforms/85xx/Kconfig
@@ -321,6 +321,23 @@ config T4240_QDS
 	help
 	  This option enables support for the T4240 QDS board
 
+config B4_QDS
+	bool "Freescale B4 QDS"
+	select DEFAULT_UIMAGE
+	select E500
+	select PPC_E500MC
+	select PHYS_64BIT
+	select SWIOTLB
+	select GENERIC_GPIO
+	select ARCH_REQUIRE_GPIOLIB
+	select HAS_RAPIDIO
+	select PPC_EPAPR_HV_PIC
+	help
+	  This option enables support for the B4 QDS board
+	  The B4 application development system B4 QDS is a complete
+	  debugging environment intended for engineers developing
+	  applications for the B4.
+
 endif
 endif # FSL_SOC_BOOKE
 
diff --git a/arch/powerpc/platforms/85xx/Makefile b/arch/powerpc/platforms/85xx/Makefile
index 712e233..2eab37e 100644
--- a/arch/powerpc/platforms/85xx/Makefile
+++ b/arch/powerpc/platforms/85xx/Makefile
@@ -23,6 +23,7 @@ obj-$(CONFIG_P4080_DS)    += p4080_ds.o corenet_ds.o
 obj-$(CONFIG_P5020_DS)    += p5020_ds.o corenet_ds.o
 obj-$(CONFIG_P5040_DS)    += p5040_ds.o corenet_ds.o
 obj-$(CONFIG_T4240_QDS)   += t4240_qds.o corenet_ds.o
+obj-$(CONFIG_B4_QDS)	  += b4_qds.o corenet_ds.o
 obj-$(CONFIG_STX_GP3)	  += stx_gp3.o
 obj-$(CONFIG_TQM85xx)	  += tqm85xx.o
 obj-$(CONFIG_SBC8548)     += sbc8548.o
diff --git a/arch/powerpc/platforms/85xx/b4_qds.c b/arch/powerpc/platforms/85xx/b4_qds.c
new file mode 100644
index 0000000..0c6702f
--- /dev/null
+++ b/arch/powerpc/platforms/85xx/b4_qds.c
@@ -0,0 +1,102 @@
+/*
+ * B4 QDS Setup
+ * Should apply for QDS platform of B4860 and it's personalities.
+ * viz B4860/B4420/B4220QDS
+ *
+ * Copyright 2012 Freescale Semiconductor Inc.
+ *
+ * This program is free software; you can redistribute  it and/or modify it
+ * under  the terms of  the GNU General  Public License as published by the
+ * Free Software Foundation;  either version 2 of the  License, or (at your
+ * option) any later version.
+ */
+
+#include <linux/kernel.h>
+#include <linux/pci.h>
+#include <linux/kdev_t.h>
+#include <linux/delay.h>
+#include <linux/interrupt.h>
+#include <linux/phy.h>
+
+#include <asm/time.h>
+#include <asm/machdep.h>
+#include <asm/pci-bridge.h>
+#include <mm/mmu_decl.h>
+#include <asm/prom.h>
+#include <asm/udbg.h>
+#include <asm/mpic.h>
+
+#include <linux/of_platform.h>
+#include <sysdev/fsl_soc.h>
+#include <sysdev/fsl_pci.h>
+#include <asm/ehv_pic.h>
+
+#include "corenet_ds.h"
+
+/*
+ * Called very early, device-tree isn't unflattened
+ */
+static int __init b4_qds_probe(void)
+{
+	unsigned long root = of_get_flat_dt_root();
+#ifdef CONFIG_SMP
+	extern struct smp_ops_t smp_85xx_ops;
+#endif
+
+	if ((of_flat_dt_is_compatible(root, "fsl,B4860QDS")) ||
+		(of_flat_dt_is_compatible(root, "fsl,B4420QDS")) ||
+			(of_flat_dt_is_compatible(root, "fsl,B4220QDS")))
+		return 1;
+
+	/* Check if we're running under the Freescale hypervisor */
+	if ((of_flat_dt_is_compatible(root, "fsl,B4860QDS-hv")) ||
+		(of_flat_dt_is_compatible(root, "fsl,B4420QDS-hv")) ||
+			(of_flat_dt_is_compatible(root, "fsl,B4220QDS-hv"))) {
+		ppc_md.init_IRQ = ehv_pic_init;
+		ppc_md.get_irq = ehv_pic_get_irq;
+		ppc_md.restart = fsl_hv_restart;
+		ppc_md.power_off = fsl_hv_halt;
+		ppc_md.halt = fsl_hv_halt;
+#ifdef CONFIG_SMP
+		/*
+		 * Disable the timebase sync operations because we can't write
+		 * to the timebase registers under the hypervisor.
+		  */
+		smp_85xx_ops.give_timebase = NULL;
+		smp_85xx_ops.take_timebase = NULL;
+#endif
+		return 1;
+	}
+
+	return 0;
+}
+
+define_machine(b4_qds) {
+	.name			= "B4 QDS",
+	.probe			= b4_qds_probe,
+	.setup_arch		= corenet_ds_setup_arch,
+	.init_IRQ		= corenet_ds_pic_init,
+#ifdef CONFIG_PCI
+	.pcibios_fixup_bus	= fsl_pcibios_fixup_bus,
+#endif
+/* coreint doesn't play nice with lazy EE, use legacy mpic for now */
+#ifdef CONFIG_PPC64
+	.get_irq		= mpic_get_irq,
+#else
+	.get_irq		= mpic_get_coreint_irq,
+#endif
+	.restart		= fsl_rstcr_restart,
+	.calibrate_decr		= generic_calibrate_decr,
+	.progress		= udbg_progress,
+#ifdef CONFIG_PPC64
+	.power_save		= book3e_idle,
+#else
+	.power_save		= e500_idle,
+#endif
+};
+
+machine_arch_initcall(b4_qds, corenet_ds_publish_devices);
+
+#ifdef CONFIG_SWIOTLB
+machine_arch_initcall(b4_qds, swiotlb_setup_bus_notifier);
+#endif
-- 
1.7.6.GIT

Re: [PATCH 4/5] powerpc/fsl-booke: Add B4_QDS board support

[Kumar Gala]

On Apr 2, 2013, at 2:16 AM, Shaveta Leekha wrote:

> - Add support for B4 board in board file b4_qds.c,
> It is common for B4860, B4420 and B4220QDS as they share same QDS =
board
> - Add B4QDS support in Kconfig and Makefile
>=20
> B4860QDS is a high-performance computing evaluation, development and
> test platform supporting the B4860 QorIQ Power Architecture processor,
> with following major features:
>=20
>   - Four dual-threaded e6500 Power Architecture processors
>     organized in one cluster-each core runs up to 1.8 GHz
>   - Two DDR3/3L controllers for high-speed memory interface each
>     runs at up to 1866.67 MHz
>   - CoreNet fabric that fully supports coherency using MESI protocol
>     between the e6500 cores, SC3900 FVP cores, memories and
>     external interfaces.
>   - Data Path Acceleration Architecture having FMAN, QMan, BMan, SEC =
5.3 and RMAN
>   - Large internal cache memory with snooping and stashing =
capabilities
>   - Sixteen 10-GHz SerDes lanes that serve:
>       - Two SRIO interfaces. Each supports up to 4 lanes and
>         a total of up to 8 lanes
>       - Up to 8-lanes Common Public Radio Interface (CPRI) controller
>         for glue-less antenna connection
>       - Two 10-Gbit Ethernet controllers (10GEC)
>       - Six 1G/2.5-Gbit Ethernet controllers for network =
communications
>       - PCI Express controller
>       - Debug (Aurora)
>   - Various system peripherals
>=20
> B4420 and B4220 have some differences in comparison to B4860 with =
fewer core/clusters(both SC3900 and e6500),
> fewer DDR controllers, fewer serdes lanes, fewer SGMII interfaces and =
reduced target frequencies.
>=20
> Key differences between B4860 and B4420:
> B4420 has:
>   - Fewer e6500 cores:
>       1 cluster with 2 e6500 cores
>   - Fewer SC3900 cores/clusters:
>       1 cluster with 2 SC3900 cores per cluster
>   - Single DDRC @ 1.6GHz
>   - 2 X 4 lane serdes
>   - 3 SGMII interfaces
>   - no sRIO
>   - no 10G
>=20
> Key differences between B4860 and B4220:
> B4220 has:
>   - Fewer e6500 cores:
>       1 cluster with 1 e6500 core
>   - Fewer SC3900 cores/clusters:
>       1 cluster with 2 SC3900 cores per cluster
>   - Single DDRC @ 1.33GHz
>   - 2 X 2 lane serdes
>   - 2 SGMII interfaces
>   - no sRIO
>   - no 10G
>=20
> Signed-off-by: Shaveta Leekha <shaveta@freescale.com>
> ---
> arch/powerpc/platforms/85xx/Kconfig  |   17 ++++++
> arch/powerpc/platforms/85xx/Makefile |    1 +
> arch/powerpc/platforms/85xx/b4_qds.c |  102 =
++++++++++++++++++++++++++++++++++
> 3 files changed, 120 insertions(+), 0 deletions(-)
> create mode 100644 arch/powerpc/platforms/85xx/b4_qds.c

commit messages should line wrap at 75 chars.

- k=

RE: [PATCH 4/5] powerpc/fsl-booke: Add B4_QDS board support

[Leekha Shaveta-B20052]

-----Original Message-----
From: Kumar Gala [mailto:galak@kernel.crashing.org]=20
Sent: Wednesday, April 03, 2013 10:12 PM
To: Leekha Shaveta-B20052
Cc: linuxppc-dev@lists.ozlabs.org
Subject: Re: [PATCH 4/5] powerpc/fsl-booke: Add B4_QDS board support


On Apr 2, 2013, at 2:16 AM, Shaveta Leekha wrote:

> - Add support for B4 board in board file b4_qds.c, It is common for=20
> B4860, B4420 and B4220QDS as they share same QDS board
> - Add B4QDS support in Kconfig and Makefile
>=20
> B4860QDS is a high-performance computing evaluation, development and=20
> test platform supporting the B4860 QorIQ Power Architecture processor,=20
> with following major features:
>=20
>   - Four dual-threaded e6500 Power Architecture processors
>     organized in one cluster-each core runs up to 1.8 GHz
>   - Two DDR3/3L controllers for high-speed memory interface each
>     runs at up to 1866.67 MHz
>   - CoreNet fabric that fully supports coherency using MESI protocol
>     between the e6500 cores, SC3900 FVP cores, memories and
>     external interfaces.
>   - Data Path Acceleration Architecture having FMAN, QMan, BMan, SEC 5.3 =
and RMAN
>   - Large internal cache memory with snooping and stashing capabilities
>   - Sixteen 10-GHz SerDes lanes that serve:
>       - Two SRIO interfaces. Each supports up to 4 lanes and
>         a total of up to 8 lanes
>       - Up to 8-lanes Common Public Radio Interface (CPRI) controller
>         for glue-less antenna connection
>       - Two 10-Gbit Ethernet controllers (10GEC)
>       - Six 1G/2.5-Gbit Ethernet controllers for network communications
>       - PCI Express controller
>       - Debug (Aurora)
>   - Various system peripherals
>=20
> B4420 and B4220 have some differences in comparison to B4860 with=20
> fewer core/clusters(both SC3900 and e6500), fewer DDR controllers, fewer =
serdes lanes, fewer SGMII interfaces and reduced target frequencies.
>=20
> Key differences between B4860 and B4420:
> B4420 has:
>   - Fewer e6500 cores:
>       1 cluster with 2 e6500 cores
>   - Fewer SC3900 cores/clusters:
>       1 cluster with 2 SC3900 cores per cluster
>   - Single DDRC @ 1.6GHz
>   - 2 X 4 lane serdes
>   - 3 SGMII interfaces
>   - no sRIO
>   - no 10G
>=20
> Key differences between B4860 and B4220:
> B4220 has:
>   - Fewer e6500 cores:
>       1 cluster with 1 e6500 core
>   - Fewer SC3900 cores/clusters:
>       1 cluster with 2 SC3900 cores per cluster
>   - Single DDRC @ 1.33GHz
>   - 2 X 2 lane serdes
>   - 2 SGMII interfaces
>   - no sRIO
>   - no 10G
>=20
> Signed-off-by: Shaveta Leekha <shaveta@freescale.com>
> ---
> arch/powerpc/platforms/85xx/Kconfig  |   17 ++++++
> arch/powerpc/platforms/85xx/Makefile |    1 +
> arch/powerpc/platforms/85xx/b4_qds.c |  102=20
> ++++++++++++++++++++++++++++++++++
> 3 files changed, 120 insertions(+), 0 deletions(-) create mode 100644=20
> arch/powerpc/platforms/85xx/b4_qds.c

commit messages should line wrap at 75 chars.

- k
[SL] Ok, will do that.
Regards,
Shaveta=20

[PATCH 5/5] powerpc/85xx: Update corenet64_smp_defconfig for B4_QDS

[Shaveta Leekha]

Signed-off-by: Shaveta Leekha <shaveta@freescale.com>
---
 arch/powerpc/configs/corenet64_smp_defconfig |    1 +
 1 files changed, 1 insertions(+), 0 deletions(-)

diff --git a/arch/powerpc/configs/corenet64_smp_defconfig b/arch/powerpc/configs/corenet64_smp_defconfig
index 1c6eb66..6c8b020 100644
--- a/arch/powerpc/configs/corenet64_smp_defconfig
+++ b/arch/powerpc/configs/corenet64_smp_defconfig
@@ -21,6 +21,7 @@ CONFIG_MODVERSIONS=y
 # CONFIG_BLK_DEV_BSG is not set
 CONFIG_PARTITION_ADVANCED=y
 CONFIG_MAC_PARTITION=y
+CONFIG_B4_QDS=y
 CONFIG_P5020_DS=y
 CONFIG_P5040_DS=y
 CONFIG_T4240_QDS=y
-- 
1.7.6.GIT

Re: [PATCH 2/5] powerpc/fsl-booke: Add initial silicon device tree files for B4860 and B4420

[Scott Wood]

On 04/02/2013 02:16:05 AM, Shaveta Leekha wrote:
> +/ {
> +	compatible =3D "fsl,B4860";
> +
> +	cpus {
> +		cpu1: PowerPC,e6500@1 {
> +			device_type =3D "cpu";
> +			reg =3D <2 3>;
> +			next-level-cache =3D <&L2>;
> +		};
> +		cpu2: PowerPC,e6500@2 {
> +			device_type =3D "cpu";
> +			reg =3D <4 5>;
> +			next-level-cache =3D <&L2>;
> +		};
> +		cpu3: PowerPC,e6500@3 {
> +			device_type =3D "cpu";
> +			reg =3D <6 7>;
> +			next-level-cache =3D <&L2>;
> +		};

The unit addresses need to match "reg".

-Scott=

RE: [PATCH 2/5] powerpc/fsl-booke: Add initial silicon device tree files for B4860 and B4420

[Leekha Shaveta-B20052]

-----Original Message-----
From: Wood Scott-B07421=20
Sent: Wednesday, April 03, 2013 12:49 AM
To: Leekha Shaveta-B20052
Cc: linuxppc-dev@lists.ozlabs.org; Zhao Chenhui-B35336; Lian Minghuan-B3193=
9; Leekha Shaveta-B20052; Garg Vakul-B16394; Tang Yuantian-B29983; Fleming =
Andy-AFLEMING; Mehresh Ramneek-B31383; Sethi Varun-B16395
Subject: Re: [PATCH 2/5] powerpc/fsl-booke: Add initial silicon device tree=
 files for B4860 and B4420

On 04/02/2013 02:16:05 AM, Shaveta Leekha wrote:
> +/ {
> +	compatible =3D "fsl,B4860";
> +
> +	cpus {
> +		cpu1: PowerPC,e6500@1 {
> +			device_type =3D "cpu";
> +			reg =3D <2 3>;
> +			next-level-cache =3D <&L2>;
> +		};
> +		cpu2: PowerPC,e6500@2 {
> +			device_type =3D "cpu";
> +			reg =3D <4 5>;
> +			next-level-cache =3D <&L2>;
> +		};
> +		cpu3: PowerPC,e6500@3 {
> +			device_type =3D "cpu";
> +			reg =3D <6 7>;
> +			next-level-cache =3D <&L2>;
> +		};

The unit addresses need to match "reg".
[SL] You mean  "@1" should match to "reg =3D <2 3>" ?
As each e6500 core in B4860 is dual- threaded, reg property here represents=
 the thread's identifier in that PA core.

So convention used in T4 and B4 is: core 0 having threads 0 and 1,
						Core 1 having <2 3> and so on....

Regards,
Shaveta



-Scott

Re: [PATCH 2/5] powerpc/fsl-booke: Add initial silicon device tree files for B4860 and B4420

[Scott Wood]

On 04/03/2013 01:42:14 AM, Leekha Shaveta-B20052 wrote:
>=20
>=20
> -----Original Message-----
> From: Wood Scott-B07421
> Sent: Wednesday, April 03, 2013 12:49 AM
> To: Leekha Shaveta-B20052
> Cc: linuxppc-dev@lists.ozlabs.org; Zhao Chenhui-B35336; Lian =20
> Minghuan-B31939; Leekha Shaveta-B20052; Garg Vakul-B16394; Tang =20
> Yuantian-B29983; Fleming Andy-AFLEMING; Mehresh Ramneek-B31383; Sethi =20
> Varun-B16395
> Subject: Re: [PATCH 2/5] powerpc/fsl-booke: Add initial silicon =20
> device tree files for B4860 and B4420
>=20
> On 04/02/2013 02:16:05 AM, Shaveta Leekha wrote:
> > +/ {
> > +	compatible =3D "fsl,B4860";
> > +
> > +	cpus {
> > +		cpu1: PowerPC,e6500@1 {
> > +			device_type =3D "cpu";
> > +			reg =3D <2 3>;
> > +			next-level-cache =3D <&L2>;
> > +		};
> > +		cpu2: PowerPC,e6500@2 {
> > +			device_type =3D "cpu";
> > +			reg =3D <4 5>;
> > +			next-level-cache =3D <&L2>;
> > +		};
> > +		cpu3: PowerPC,e6500@3 {
> > +			device_type =3D "cpu";
> > +			reg =3D <6 7>;
> > +			next-level-cache =3D <&L2>;
> > +		};
>=20
> The unit addresses need to match "reg".
> [SL] You mean  "@1" should match to "reg =3D <2 3>" ?

Yes, it should be "@2" for that node.

> As each e6500 core in B4860 is dual- threaded, reg property here =20
> represents the thread's identifier in that PA core.
>=20
> So convention used in T4 and B4 is: core 0 having threads 0 and 1,
> 						Core 1 having <2 3> and =20
> so on....

The convention used in device trees is that the unit address matches =20
the reg.

-Scott=

RE: [PATCH 2/5] powerpc/fsl-booke: Add initial silicon device tree files for B4860 and B4420

[Leekha Shaveta-B20052]

-----Original Message-----
From: Wood Scott-B07421=20
Sent: Wednesday, April 03, 2013 10:10 PM
To: Leekha Shaveta-B20052
Cc: Wood Scott-B07421; linuxppc-dev@lists.ozlabs.org; Zhao Chenhui-B35336; =
Lian Minghuan-B31939; Garg Vakul-B16394; Tang Yuantian-B29983; Fleming Andy=
-AFLEMING; Mehresh Ramneek-B31383; Sethi Varun-B16395
Subject: Re: [PATCH 2/5] powerpc/fsl-booke: Add initial silicon device tree=
 files for B4860 and B4420

On 04/03/2013 01:42:14 AM, Leekha Shaveta-B20052 wrote:
>=20
>=20
> -----Original Message-----
> From: Wood Scott-B07421
> Sent: Wednesday, April 03, 2013 12:49 AM
> To: Leekha Shaveta-B20052
> Cc: linuxppc-dev@lists.ozlabs.org; Zhao Chenhui-B35336; Lian=20
> Minghuan-B31939; Leekha Shaveta-B20052; Garg Vakul-B16394; Tang=20
> Yuantian-B29983; Fleming Andy-AFLEMING; Mehresh Ramneek-B31383; Sethi
> Varun-B16395
> Subject: Re: [PATCH 2/5] powerpc/fsl-booke: Add initial silicon device=20
> tree files for B4860 and B4420
>=20
> On 04/02/2013 02:16:05 AM, Shaveta Leekha wrote:
> > +/ {
> > +	compatible =3D "fsl,B4860";
> > +
> > +	cpus {
> > +		cpu1: PowerPC,e6500@1 {
> > +			device_type =3D "cpu";
> > +			reg =3D <2 3>;
> > +			next-level-cache =3D <&L2>;
> > +		};
> > +		cpu2: PowerPC,e6500@2 {
> > +			device_type =3D "cpu";
> > +			reg =3D <4 5>;
> > +			next-level-cache =3D <&L2>;
> > +		};
> > +		cpu3: PowerPC,e6500@3 {
> > +			device_type =3D "cpu";
> > +			reg =3D <6 7>;
> > +			next-level-cache =3D <&L2>;
> > +		};
>=20
> The unit addresses need to match "reg".
> [SL] You mean  "@1" should match to "reg =3D <2 3>" ?

Yes, it should be "@2" for that node.

> As each e6500 core in B4860 is dual- threaded, reg property here=20
> represents the thread's identifier in that PA core.
>=20
> So convention used in T4 and B4 is: core 0 having threads 0 and 1,
> 						Core 1 having <2 3> and
> so on....

The convention used in device trees is that the unit address matches the re=
g.

-Scott
[SL] Ok, I can change that. Will make unit address as @2 for <2 3>, @4 for =
<4 5> and so on....

Kumar, please respond here, as I have followed the convention used in T4 de=
vice tree files for
Dual-threaded cores.

Regards,
Shaveta

Re: [PATCH 2/5] powerpc/fsl-booke: Add initial silicon device tree files for B4860 and B4420

[Kumar Gala]

On Apr 4, 2013, at 2:03 AM, Leekha Shaveta-B20052 wrote:

>=20
>=20
> -----Original Message-----
> From: Wood Scott-B07421=20
> Sent: Wednesday, April 03, 2013 10:10 PM
> To: Leekha Shaveta-B20052
> Cc: Wood Scott-B07421; linuxppc-dev@lists.ozlabs.org; Zhao =
Chenhui-B35336; Lian Minghuan-B31939; Garg Vakul-B16394; Tang =
Yuantian-B29983; Fleming Andy-AFLEMING; Mehresh Ramneek-B31383; Sethi =
Varun-B16395
> Subject: Re: [PATCH 2/5] powerpc/fsl-booke: Add initial silicon device =
tree files for B4860 and B4420
>=20
> On 04/03/2013 01:42:14 AM, Leekha Shaveta-B20052 wrote:
>>=20
>>=20
>> -----Original Message-----
>> From: Wood Scott-B07421
>> Sent: Wednesday, April 03, 2013 12:49 AM
>> To: Leekha Shaveta-B20052
>> Cc: linuxppc-dev@lists.ozlabs.org; Zhao Chenhui-B35336; Lian=20
>> Minghuan-B31939; Leekha Shaveta-B20052; Garg Vakul-B16394; Tang=20
>> Yuantian-B29983; Fleming Andy-AFLEMING; Mehresh Ramneek-B31383; Sethi
>> Varun-B16395
>> Subject: Re: [PATCH 2/5] powerpc/fsl-booke: Add initial silicon =
device=20
>> tree files for B4860 and B4420
>>=20
>> On 04/02/2013 02:16:05 AM, Shaveta Leekha wrote:
>>> +/ {
>>> +	compatible =3D "fsl,B4860";
>>> +
>>> +	cpus {
>>> +		cpu1: PowerPC,e6500@1 {
>>> +			device_type =3D "cpu";
>>> +			reg =3D <2 3>;
>>> +			next-level-cache =3D <&L2>;
>>> +		};
>>> +		cpu2: PowerPC,e6500@2 {
>>> +			device_type =3D "cpu";
>>> +			reg =3D <4 5>;
>>> +			next-level-cache =3D <&L2>;
>>> +		};
>>> +		cpu3: PowerPC,e6500@3 {
>>> +			device_type =3D "cpu";
>>> +			reg =3D <6 7>;
>>> +			next-level-cache =3D <&L2>;
>>> +		};
>>=20
>> The unit addresses need to match "reg".
>> [SL] You mean  "@1" should match to "reg =3D <2 3>" ?
>=20
> Yes, it should be "@2" for that node.
>=20
>> As each e6500 core in B4860 is dual- threaded, reg property here=20
>> represents the thread's identifier in that PA core.
>>=20
>> So convention used in T4 and B4 is: core 0 having threads 0 and 1,
>> 						Core 1 having <2 3> and
>> so on....
>=20
> The convention used in device trees is that the unit address matches =
the reg.
>=20
> -Scott
> [SL] Ok, I can change that. Will make unit address as @2 for <2 3>, @4 =
for <4 5> and so on....
>=20
> Kumar, please respond here, as I have followed the convention used in =
T4 device tree files for
> Dual-threaded cores.

Scott is correct, we probably need to fix the T4 dts.

- k=

RE: [PATCH 2/5] powerpc/fsl-booke: Add initial silicon device tree files for B4860 and B4420

[Leekha Shaveta-B20052]

-----Original Message-----
From: Kumar Gala [mailto:galak@kernel.crashing.org]=20
Sent: Friday, April 05, 2013 12:44 AM
To: Leekha Shaveta-B20052
Cc: Wood Scott-B07421; Zhao Chenhui-B35336; Mehresh Ramneek-B31383; Garg Va=
kul-B16394; Lian Minghuan-B31939; Tang Yuantian-B29983; Fleming Andy-AFLEMI=
NG; Sethi Varun-B16395; linuxppc-dev@lists.ozlabs.org
Subject: Re: [PATCH 2/5] powerpc/fsl-booke: Add initial silicon device tree=
 files for B4860 and B4420


On Apr 4, 2013, at 2:03 AM, Leekha Shaveta-B20052 wrote:

>=20
>=20
> -----Original Message-----
> From: Wood Scott-B07421
> Sent: Wednesday, April 03, 2013 10:10 PM
> To: Leekha Shaveta-B20052
> Cc: Wood Scott-B07421; linuxppc-dev@lists.ozlabs.org; Zhao=20
> Chenhui-B35336; Lian Minghuan-B31939; Garg Vakul-B16394; Tang=20
> Yuantian-B29983; Fleming Andy-AFLEMING; Mehresh Ramneek-B31383; Sethi=20
> Varun-B16395
> Subject: Re: [PATCH 2/5] powerpc/fsl-booke: Add initial silicon device=20
> tree files for B4860 and B4420
>=20
> On 04/03/2013 01:42:14 AM, Leekha Shaveta-B20052 wrote:
>>=20
>>=20
>> -----Original Message-----
>> From: Wood Scott-B07421
>> Sent: Wednesday, April 03, 2013 12:49 AM
>> To: Leekha Shaveta-B20052
>> Cc: linuxppc-dev@lists.ozlabs.org; Zhao Chenhui-B35336; Lian=20
>> Minghuan-B31939; Leekha Shaveta-B20052; Garg Vakul-B16394; Tang=20
>> Yuantian-B29983; Fleming Andy-AFLEMING; Mehresh Ramneek-B31383; Sethi
>> Varun-B16395
>> Subject: Re: [PATCH 2/5] powerpc/fsl-booke: Add initial silicon=20
>> device tree files for B4860 and B4420
>>=20
>> On 04/02/2013 02:16:05 AM, Shaveta Leekha wrote:
>>> +/ {
>>> +	compatible =3D "fsl,B4860";
>>> +
>>> +	cpus {
>>> +		cpu1: PowerPC,e6500@1 {
>>> +			device_type =3D "cpu";
>>> +			reg =3D <2 3>;
>>> +			next-level-cache =3D <&L2>;
>>> +		};
>>> +		cpu2: PowerPC,e6500@2 {
>>> +			device_type =3D "cpu";
>>> +			reg =3D <4 5>;
>>> +			next-level-cache =3D <&L2>;
>>> +		};
>>> +		cpu3: PowerPC,e6500@3 {
>>> +			device_type =3D "cpu";
>>> +			reg =3D <6 7>;
>>> +			next-level-cache =3D <&L2>;
>>> +		};
>>=20
>> The unit addresses need to match "reg".
>> [SL] You mean  "@1" should match to "reg =3D <2 3>" ?
>=20
> Yes, it should be "@2" for that node.
>=20
>> As each e6500 core in B4860 is dual- threaded, reg property here=20
>> represents the thread's identifier in that PA core.
>>=20
>> So convention used in T4 and B4 is: core 0 having threads 0 and 1,
>> 						Core 1 having <2 3> and
>> so on....
>=20
> The convention used in device trees is that the unit address matches the =
reg.
>=20
> -Scott
> [SL] Ok, I can change that. Will make unit address as @2 for <2 3>, @4 fo=
r <4 5> and so on....
>=20
> Kumar, please respond here, as I have followed the convention used in=20
> T4 device tree files for Dual-threaded cores.

Scott is correct, we probably need to fix the T4 dts.

- k
[SL] ok, will do it for B4
Regards,
Shaveta=20

Re: [PATCH 2/5] powerpc/fsl-booke: Add initial silicon device tree files for B4860 and B4420

[Kumar Gala]

On Apr 2, 2013, at 2:16 AM, Shaveta Leekha wrote:

> B4860 and B4420 are similar that share some commonalities
>=20
> * common features have been added in b4si-pre.dtsi and b4si-post.dtsi
> * differences are added in respective silicon files of B4860 and B4420

What are the differences between B4860 & B4420, beyond # of cores?

>=20
> There are several things missing from the device trees of B4860 and =
B4420:
>=20
> * DPAA related nodes (Qman, Bman, Fman, Rman)
> * DSP related nodes/information

What about:

serdes, sfp [security fuse processor], thermal, gpio, maple, cpri, quad =
timers,=20

>=20
> Signed-off-by: Shaveta Leekha <shaveta@freescale.com>
> Signed-off-by: Zhao Chenhui <chenhui.zhao@freescale.com>
> Signed-off-by: Li Yang <leoli@freescale.com>
> Signed-off-by: Tang Yuantian <Yuantian.Tang@freescale.com>
> Signed-off-by: Varun Sethi <Varun.Sethi@freescale.com>
> Signed-off-by: Minghuan Lian <Minghuan.Lian@freescale.com>
> Signed-off-by: Ramneek Mehresh <ramneek.mehresh@freescale.com>
> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
> Signed-off-by: Andy Fleming <afleming@freescale.com>
> Signed-off-by: Vakul Garg <vakul@freescale.com>
> ---
> arch/powerpc/boot/dts/fsl/b4420si-post.dtsi |   94 ++++++++++
> arch/powerpc/boot/dts/fsl/b4420si-pre.dtsi  |   49 +++++
> arch/powerpc/boot/dts/fsl/b4860si-post.dtsi |  138 ++++++++++++++
> arch/powerpc/boot/dts/fsl/b4860si-pre.dtsi  |   59 ++++++
> arch/powerpc/boot/dts/fsl/b4si-post.dtsi    |  262 =
+++++++++++++++++++++++++++
> arch/powerpc/boot/dts/fsl/b4si-pre.dtsi     |   65 +++++++

Remove b4si-pre.dtsi, there isn't enough here to warrant not just =
merging it into b4420si-pre.dtsi & b4860si-pre.dtsi

> 6 files changed, 667 insertions(+), 0 deletions(-)
> create mode 100644 arch/powerpc/boot/dts/fsl/b4420si-post.dtsi
> create mode 100644 arch/powerpc/boot/dts/fsl/b4420si-pre.dtsi
> create mode 100644 arch/powerpc/boot/dts/fsl/b4860si-post.dtsi
> create mode 100644 arch/powerpc/boot/dts/fsl/b4860si-pre.dtsi
> create mode 100644 arch/powerpc/boot/dts/fsl/b4si-post.dtsi
> create mode 100644 arch/powerpc/boot/dts/fsl/b4si-pre.dtsi
>=20
> diff --git a/arch/powerpc/boot/dts/fsl/b4420si-post.dtsi =
b/arch/powerpc/boot/dts/fsl/b4420si-post.dtsi
> new file mode 100644
> index 0000000..bba0c03
> --- /dev/null
> +++ b/arch/powerpc/boot/dts/fsl/b4420si-post.dtsi
> @@ -0,0 +1,94 @@
> +/*
> + * B4420 Silicon/SoC Device Tree Source (post include)
> + *
> + * Copyright 2012 Freescale Semiconductor, Inc.
> + *
> + * Redistribution and use in source and binary forms, with or without
> + * modification, are permitted provided that the following conditions =
are met:
> + *     * Redistributions of source code must retain the above =
copyright
> + *       notice, this list of conditions and the following =
disclaimer.
> + *     * Redistributions in binary form must reproduce the above =
copyright
> + *       notice, this list of conditions and the following disclaimer =
in the
> + *       documentation and/or other materials provided with the =
distribution.
> + *     * Neither the name of Freescale Semiconductor nor the
> + *       names of its contributors may be used to endorse or promote =
products
> + *       derived from this software without specific prior written =
permission.
> + *
> + *
> + * ALTERNATIVELY, this software may be distributed under the terms of =
the
> + * GNU General Public License ("GPL") as published by the Free =
Software
> + * Foundation, either version 2 of that License or (at your option) =
any
> + * later version.
> + *
> + * This software is provided by Freescale Semiconductor "as is" and =
any
> + * express or implied warranties, including, but not limited to, the =
implied
> + * warranties of merchantability and fitness for a particular purpose =
are
> + * disclaimed. In no event shall Freescale Semiconductor be liable =
for any
> + * direct, indirect, incidental, special, exemplary, or consequential =
damages
> + * (including, but not limited to, procurement of substitute goods or =
services;
> + * loss of use, data, or profits; or business interruption) however =
caused and
> + * on any theory of liability, whether in contract, strict liability, =
or tort
> + * (including negligence or otherwise) arising in any way out of the =
use of
> + * this software, even if advised of the possibility of such damage.
> + */
> +
> +/include/ "b4si-post.dtsi"
> +
> +/* controller at 0x200000 */
> +&pci0 {
> +	compatible =3D "fsl,b4420-pcie", "fsl,qoriq-pcie-v2.4";
> +};
> +
> +&dcsr {
> +	dcsr-epu@0 {
> +		compatible =3D "fsl,b4420-dcsr-epu", "fsl,dcsr-epu";
> +	};
> +	dcsr-npc {
> +		compatible =3D "fsl,b4420-dcsr-cnpc", "fsl,dcsr-cnpc";
> +	};
> +	dcsr-dpaa@9000 {
> +		compatible =3D "fsl,b4420-dcsr-dpaa", "fsl,dcsr-dpaa";
> +	};
> +	dcsr-ocn@11000 {
> +		compatible =3D "fsl,b4420-dcsr-ocn", "fsl,dcsr-ocn";
> +	};
> +	dcsr-nal@18000 {
> +		compatible =3D "fsl,b4420-dcsr-nal", "fsl,dcsr-nal";
> +	};
> +	dcsr-rcpm@22000 {
> +		compatible =3D "fsl,b4420-dcsr-rcpm", "fsl,dcsr-rcpm";
> +	};
> +	dcsr-snpc@30000 {
> +		compatible =3D "fsl,b4420-dcsr-snpc", "fsl,dcsr-snpc";
> +	};
> +	dcsr-snpc@31000 {
> +		compatible =3D "fsl,b4420-dcsr-snpc", "fsl,dcsr-snpc";
> +	};
> +	dcsr-cpu-sb-proxy@108000 {
> +		compatible =3D "fsl,dcsr-e6500-sb-proxy", =
"fsl,dcsr-cpu-sb-proxy";
> +		cpu-handle =3D <&cpu1>;
> +		reg =3D <0x108000 0x1000 0x109000 0x1000>;
> +	};
> +};
> +
> +&soc {
> +	cpc: l3-cache-controller@10000 {
> +		compatible =3D "fsl,b4420-l3-cache-controller", "cache";
> +	};
> +
> +	corenet-cf@18000 {
> +		compatible =3D "fsl,b4420-corenet-cf";
> +	};
> +
> +	guts: global-utilities@e0000 {
> +		compatible =3D "fsl,b4420-device-config", =
"fsl,qoriq-device-config-2.0";
> +	};
> +
> +	clockgen: global-utilities@e1000 {
> +		compatible =3D "fsl,b4420-clockgen", =
"fsl,qoriq-clockgen-2";
> +	};
> +
> +	L2: l2-cache-controller@c20000 {
> +		compatible =3D "fsl,b4420-l2-cache-controller";
> +	};
> +};
> diff --git a/arch/powerpc/boot/dts/fsl/b4420si-pre.dtsi =
b/arch/powerpc/boot/dts/fsl/b4420si-pre.dtsi
> new file mode 100644
> index 0000000..555b0e4
> --- /dev/null
> +++ b/arch/powerpc/boot/dts/fsl/b4420si-pre.dtsi
> @@ -0,0 +1,49 @@
> +/*
> + * B4420 Silicon/SoC Device Tree Source (pre include)
> + *
> + * Copyright 2012 Freescale Semiconductor, Inc.
> + *
> + * Redistribution and use in source and binary forms, with or without
> + * modification, are permitted provided that the following conditions =
are met:
> + *     * Redistributions of source code must retain the above =
copyright
> + *       notice, this list of conditions and the following =
disclaimer.
> + *     * Redistributions in binary form must reproduce the above =
copyright
> + *       notice, this list of conditions and the following disclaimer =
in the
> + *       documentation and/or other materials provided with the =
distribution.
> + *     * Neither the name of Freescale Semiconductor nor the
> + *       names of its contributors may be used to endorse or promote =
products
> + *       derived from this software without specific prior written =
permission.
> + *
> + *
> + * ALTERNATIVELY, this software may be distributed under the terms of =
the
> + * GNU General Public License ("GPL") as published by the Free =
Software
> + * Foundation, either version 2 of that License or (at your option) =
any
> + * later version.
> + *
> + * This software is provided by Freescale Semiconductor "as is" and =
any
> + * express or implied warranties, including, but not limited to, the =
implied
> + * warranties of merchantability and fitness for a particular purpose =
are
> + * disclaimed. In no event shall Freescale Semiconductor be liable =
for any
> + * direct, indirect, incidental, special, exemplary, or consequential =
damages
> + * (including, but not limited to, procurement of substitute goods or =
services;
> + * loss of use, data, or profits; or business interruption) however =
caused and
> + * on any theory of liability, whether in contract, strict liability, =
or tort
> + * (including negligence or otherwise) arising in any way out of the =
use of
> + * this software, even if advised of the possibility of such damage.
> + */
> +
> +/dts-v1/;
> +
> +/include/ "b4si-pre.dtsi"
> +
> +/ {
> +	compatible =3D "fsl,B4420";
> +
> +	cpus {
> +		cpu1: PowerPC,e6500@1 {
> +			device_type =3D "cpu";
> +			reg =3D <2 3>;
> +			next-level-cache =3D <&L2>;
> +		};
> +	};
> +};
> diff --git a/arch/powerpc/boot/dts/fsl/b4860si-post.dtsi =
b/arch/powerpc/boot/dts/fsl/b4860si-post.dtsi
> new file mode 100644
> index 0000000..f43910f
> --- /dev/null
> +++ b/arch/powerpc/boot/dts/fsl/b4860si-post.dtsi
> @@ -0,0 +1,138 @@
> +/*
> + * B4860 Silicon/SoC Device Tree Source (post include)
> + *
> + * Copyright 2012 Freescale Semiconductor Inc.
> + *
> + * Redistribution and use in source and binary forms, with or without
> + * modification, are permitted provided that the following conditions =
are met:
> + *     * Redistributions of source code must retain the above =
copyright
> + *       notice, this list of conditions and the following =
disclaimer.
> + *     * Redistributions in binary form must reproduce the above =
copyright
> + *       notice, this list of conditions and the following disclaimer =
in the
> + *       documentation and/or other materials provided with the =
distribution.
> + *     * Neither the name of Freescale Semiconductor nor the
> + *       names of its contributors may be used to endorse or promote =
products
> + *       derived from this software without specific prior written =
permission.
> + *
> + *
> + * ALTERNATIVELY, this software may be distributed under the terms of =
the
> + * GNU General Public License ("GPL") as published by the Free =
Software
> + * Foundation, either version 2 of that License or (at your option) =
any
> + * later version.
> + *
> + * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND =
ANY
> + * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE =
IMPLIED
> + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE =
ARE
> + * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE =
FOR ANY
> + * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL =
DAMAGES
> + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR =
SERVICES;
> + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER =
CAUSED AND
> + * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, =
OR TORT
> + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE =
USE OF THIS
> + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
> + */
> +
> +/include/ "b4si-post.dtsi"
> +
> +/* controller at 0x200000 */
> +&pci0 {
> +	compatible =3D "fsl,b4860-pcie", "fsl,qoriq-pcie-v2.4";
> +};
> +
> +&rio {
> +	compatible =3D "fsl,srio";
> +	interrupts =3D <16 2 1 11>;
> +	#address-cells =3D <2>;
> +	#size-cells =3D <2>;
> +	fsl,iommu-parent =3D <&pamu0>;
> +	ranges;
> +
> +	port1 {
> +		#address-cells =3D <2>;
> +		#size-cells =3D <2>;
> +		cell-index =3D <1>;
> +		fsl,liodn-reg =3D <&guts 0x510>; /* RIO1LIODNR */
> +	};
> +
> +	port2 {
> +		#address-cells =3D <2>;
> +		#size-cells =3D <2>;
> +		cell-index =3D <2>;
> +		fsl,liodn-reg =3D <&guts 0x514>; /* RIO2LIODNR */
> +	};
> +};
> +
> +&dcsr {
> +	dcsr-epu@0 {
> +		compatible =3D "fsl,b4860-dcsr-epu", "fsl,dcsr-epu";
> +	};
> +	dcsr-npc {
> +		compatible =3D "fsl,b4860-dcsr-cnpc", "fsl,dcsr-cnpc";
> +	};
> +	dcsr-dpaa@9000 {
> +		compatible =3D "fsl,b4860-dcsr-dpaa", "fsl,dcsr-dpaa";
> +	};
> +	dcsr-ocn@11000 {
> +		compatible =3D "fsl,b4860-dcsr-ocn", "fsl,dcsr-ocn";
> +	};
> +	dcsr-ddr@13000 {
> +		compatible =3D "fsl,dcsr-ddr";
> +		dev-handle =3D <&ddr2>;
> +		reg =3D <0x13000 0x1000>;
> +	};
> +	dcsr-nal@18000 {
> +		compatible =3D "fsl,b4860-dcsr-nal", "fsl,dcsr-nal";
> +	};
> +	dcsr-rcpm@22000 {
> +		compatible =3D "fsl,b4860-dcsr-rcpm", "fsl,dcsr-rcpm";
> +	};
> +	dcsr-snpc@30000 {
> +		compatible =3D "fsl,b4860-dcsr-snpc", "fsl,dcsr-snpc";
> +	};
> +	dcsr-snpc@31000 {
> +		compatible =3D "fsl,b4860-dcsr-snpc", "fsl,dcsr-snpc";
> +	};
> +	dcsr-cpu-sb-proxy@108000 {
> +		compatible =3D "fsl,dcsr-e6500-sb-proxy", =
"fsl,dcsr-cpu-sb-proxy";
> +		cpu-handle =3D <&cpu1>;
> +		reg =3D <0x108000 0x1000 0x109000 0x1000>;
> +	};
> +	dcsr-cpu-sb-proxy@110000 {
> +		compatible =3D "fsl,dcsr-e6500-sb-proxy", =
"fsl,dcsr-cpu-sb-proxy";
> +		cpu-handle =3D <&cpu2>;
> +		reg =3D <0x110000 0x1000 0x111000 0x1000>;
> +	};
> +	dcsr-cpu-sb-proxy@118000 {
> +		compatible =3D "fsl,dcsr-e6500-sb-proxy", =
"fsl,dcsr-cpu-sb-proxy";
> +		cpu-handle =3D <&cpu3>;
> +		reg =3D <0x118000 0x1000 0x119000 0x1000>;
> +	};
> +};
> +
> +&soc {
> +	ddr2: memory-controller@9000 {
> +		compatible =3D "fsl,qoriq-memory-controller-v4.5", =
"fsl,qoriq-memory-controller";
> +		reg =3D <0x9000 0x1000>;
> +		interrupts =3D <16 2 1 9>;
> +	};
> +
> +	cpc: l3-cache-controller@10000 {
> +		compatible =3D "fsl,b4860-l3-cache-controller", "cache";
> +	};
> +
> +	corenet-cf@18000 {
> +		compatible =3D "fsl,b4860-corenet-cf";
> +	};
> +
> +	guts: global-utilities@e0000 {
> +		compatible =3D "fsl,b4860-device-config", =
"fsl,qoriq-device-config-2.0";
> +	};
> +
> +	clockgen: global-utilities@e1000 {
> +		compatible =3D "fsl,b4860-clockgen", =
"fsl,qoriq-clockgen-2";
> +	};
> +
> +	L2: l2-cache-controller@c20000 {
> +		compatible =3D "fsl,b4860-l2-cache-controller";
> +	};
> +};
> diff --git a/arch/powerpc/boot/dts/fsl/b4860si-pre.dtsi =
b/arch/powerpc/boot/dts/fsl/b4860si-pre.dtsi
> new file mode 100644
> index 0000000..f5737a0
> --- /dev/null
> +++ b/arch/powerpc/boot/dts/fsl/b4860si-pre.dtsi
> @@ -0,0 +1,59 @@
> +/*
> + * B4860 Silicon/SoC Device Tree Source (pre include)
> + *
> + * Copyright 2012 Freescale Semiconductor Inc.
> + *
> + * Redistribution and use in source and binary forms, with or without
> + * modification, are permitted provided that the following conditions =
are met:
> + *     * Redistributions of source code must retain the above =
copyright
> + *       notice, this list of conditions and the following =
disclaimer.
> + *     * Redistributions in binary form must reproduce the above =
copyright
> + *       notice, this list of conditions and the following disclaimer =
in the
> + *       documentation and/or other materials provided with the =
distribution.
> + *     * Neither the name of Freescale Semiconductor nor the
> + *       names of its contributors may be used to endorse or promote =
products
> + *       derived from this software without specific prior written =
permission.
> + *
> + *
> + * ALTERNATIVELY, this software may be distributed under the terms of =
the
> + * GNU General Public License ("GPL") as published by the Free =
Software
> + * Foundation, either version 2 of that License or (at your option) =
any
> + * later version.
> + *
> + * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND =
ANY
> + * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE =
IMPLIED
> + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE =
ARE
> + * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE =
FOR ANY
> + * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL =
DAMAGES
> + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR =
SERVICES;
> + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER =
CAUSED AND
> + * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, =
OR TORT
> + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE =
USE OF THIS
> + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
> + */
> +
> +/dts-v1/;
> +
> +/include/ "b4si-pre.dtsi"
> +
> +/ {
> +	compatible =3D "fsl,B4860";
> +
> +	cpus {
> +		cpu1: PowerPC,e6500@1 {
> +			device_type =3D "cpu";
> +			reg =3D <2 3>;
> +			next-level-cache =3D <&L2>;
> +		};
> +		cpu2: PowerPC,e6500@2 {
> +			device_type =3D "cpu";
> +			reg =3D <4 5>;
> +			next-level-cache =3D <&L2>;
> +		};
> +		cpu3: PowerPC,e6500@3 {
> +			device_type =3D "cpu";
> +			reg =3D <6 7>;
> +			next-level-cache =3D <&L2>;
> +		};
> +	};
> +};
> diff --git a/arch/powerpc/boot/dts/fsl/b4si-post.dtsi =
b/arch/powerpc/boot/dts/fsl/b4si-post.dtsi
> new file mode 100644
> index 0000000..06c97a2
> --- /dev/null
> +++ b/arch/powerpc/boot/dts/fsl/b4si-post.dtsi
> @@ -0,0 +1,262 @@
> +/*
> + * B4420 Silicon/SoC Device Tree Source (post include)
> + *
> + * Copyright 2012 Freescale Semiconductor, Inc.
> + *
> + * Redistribution and use in source and binary forms, with or without
> + * modification, are permitted provided that the following conditions =
are met:
> + *     * Redistributions of source code must retain the above =
copyright
> + *       notice, this list of conditions and the following =
disclaimer.
> + *     * Redistributions in binary form must reproduce the above =
copyright
> + *       notice, this list of conditions and the following disclaimer =
in the
> + *       documentation and/or other materials provided with the =
distribution.
> + *     * Neither the name of Freescale Semiconductor nor the
> + *       names of its contributors may be used to endorse or promote =
products
> + *       derived from this software without specific prior written =
permission.
> + *
> + *
> + * ALTERNATIVELY, this software may be distributed under the terms of =
the
> + * GNU General Public License ("GPL") as published by the Free =
Software
> + * Foundation, either version 2 of that License or (at your option) =
any
> + * later version.
> + *
> + * This software is provided by Freescale Semiconductor "as is" and =
any
> + * express or implied warranties, including, but not limited to, the =
implied
> + * warranties of merchantability and fitness for a particular purpose =
are
> + * disclaimed. In no event shall Freescale Semiconductor be liable =
for any
> + * direct, indirect, incidental, special, exemplary, or consequential =
damages
> + * (including, but not limited to, procurement of substitute goods or =
services;
> + * loss of use, data, or profits; or business interruption) however =
caused and
> + * on any theory of liability, whether in contract, strict liability, =
or tort
> + * (including negligence or otherwise) arising in any way out of the =
use of
> + * this software, even if advised of the possibility of such damage.
> + */
> +
> +&ifc {
> +	#address-cells =3D <2>;
> +	#size-cells =3D <1>;
> +	compatible =3D "fsl,ifc", "simple-bus";
> +	interrupts =3D <25 2 0 0>;
> +};
> +
> +/* controller at 0x200000 */
> +&pci0 {
> +	compatible =3D "fsl,b4-pcie", "fsl,qoriq-pcie-v2.4";
> +	device_type =3D "pci";
> +	#size-cells =3D <2>;
> +	#address-cells =3D <3>;
> +	bus-range =3D <0x0 0xff>;
> +	interrupts =3D <20 2 0 0>;
> +	fsl,iommu-parent =3D <&pamu0>;
> +	pcie@0 {
> +		#interrupt-cells =3D <1>;
> +		#size-cells =3D <2>;
> +		#address-cells =3D <3>;
> +		device_type =3D "pci";
> +		interrupts =3D <20 2 0 0>;
> +		interrupt-map-mask =3D <0xf800 0 0 7>;
> +		interrupt-map =3D <
> +			/* IDSEL 0x0 */
> +			0000 0 0 1 &mpic 40 1 0 0
> +			0000 0 0 2 &mpic 1 1 0 0
> +			0000 0 0 3 &mpic 2 1 0 0
> +			0000 0 0 4 &mpic 3 1 0 0
> +			>;
> +	};
> +};
> +
> +&dcsr {
> +	#address-cells =3D <1>;
> +	#size-cells =3D <1>;
> +	compatible =3D "fsl,dcsr", "simple-bus";
> +
> +	dcsr-epu@0 {
> +		compatible =3D "fsl,b4-dcsr-epu", "fsl,dcsr-epu";
> +		interrupts =3D <52 2 0 0
> +			      84 2 0 0
> +			      85 2 0 0
> +			      94 2 0 0
> +			      95 2 0 0>;
> +		reg =3D <0x0 0x1000>;
> +	};
> +	dcsr-npc {
> +		compatible =3D "fsl,b4-dcsr-cnpc", "fsl,dcsr-cnpc";
> +		reg =3D <0x1000 0x1000 0x1002000 0x10000>;
> +	};
> +	dcsr-nxc@2000 {
> +		compatible =3D "fsl,dcsr-nxc";
> +		reg =3D <0x2000 0x1000>;
> +	};
> +	dcsr-corenet {
> +		compatible =3D "fsl,dcsr-corenet";
> +		reg =3D <0x8000 0x1000 0x1A000 0x1000>;
> +	};
> +	dcsr-dpaa@9000 {
> +		compatible =3D "fsl,b4-dcsr-dpaa", "fsl,dcsr-dpaa";
> +		reg =3D <0x9000 0x1000>;
> +	};
> +	dcsr-ocn@11000 {
> +		compatible =3D "fsl,b4-dcsr-ocn", "fsl,dcsr-ocn";
> +		reg =3D <0x11000 0x1000>;
> +	};
> +	dcsr-ddr@12000 {
> +		compatible =3D "fsl,dcsr-ddr";
> +		dev-handle =3D <&ddr1>;
> +		reg =3D <0x12000 0x1000>;
> +	};
> +	dcsr-nal@18000 {
> +		compatible =3D "fsl,b4-dcsr-nal", "fsl,dcsr-nal";
> +		reg =3D <0x18000 0x1000>;
> +	};
> +	dcsr-rcpm@22000 {
> +		compatible =3D "fsl,b4-dcsr-rcpm", "fsl,dcsr-rcpm";
> +		reg =3D <0x22000 0x1000>;
> +	};
> +	dcsr-snpc@30000 {
> +		compatible =3D "fsl,b4-dcsr-snpc", "fsl,dcsr-snpc";
> +		reg =3D <0x30000 0x1000 0x1022000 0x10000>;
> +	};
> +	dcsr-snpc@31000 {
> +		compatible =3D "fsl,b4-dcsr-snpc", "fsl,dcsr-snpc";
> +		reg =3D <0x31000 0x1000 0x1042000 0x10000>;
> +	};
> +	dcsr-cpu-sb-proxy@100000 {
> +		compatible =3D "fsl,dcsr-e6500-sb-proxy", =
"fsl,dcsr-cpu-sb-proxy";
> +		cpu-handle =3D <&cpu0>;
> +		reg =3D <0x100000 0x1000 0x101000 0x1000>;
> +	};
> +};
> +
> +&soc {
> +	#address-cells =3D <1>;
> +	#size-cells =3D <1>;
> +	device_type =3D "soc";
> +	compatible =3D "simple-bus";
> +
> +	soc-sram-error {
> +		compatible =3D "fsl,soc-sram-error";
> +		interrupts =3D <16 2 1 2>;
> +	};
> +
> +	corenet-law@0 {
> +		compatible =3D "fsl,corenet-law";
> +		reg =3D <0x0 0x1000>;
> +		fsl,num-laws =3D <32>;
> +	};
> +
> +	ddr1: memory-controller@8000 {
> +		compatible =3D "fsl,qoriq-memory-controller-v4.5", =
"fsl,qoriq-memory-controller";
> +		reg =3D <0x8000 0x1000>;
> +		interrupts =3D <16 2 1 8>;
> +	};
> +
> +	cpc: l3-cache-controller@10000 {
> +		compatible =3D "fsl,b4-l3-cache-controller", "cache";
> +		reg =3D <0x10000 0x1000>;
> +		interrupts =3D <16 2 1 4>;
> +	};
> +
> +	corenet-cf@18000 {
> +		compatible =3D "fsl,b4-corenet-cf";
> +		reg =3D <0x18000 0x1000>;
> +		interrupts =3D <16 2 1 0>;
> +		fsl,ccf-num-csdids =3D <32>;
> +		fsl,ccf-num-snoopids =3D <32>;
> +	};
> +
> +	iommu@20000 {
> +		compatible =3D  "fsl,pamu-v1.0", "fsl,pamu";
> +		reg =3D <0x20000 0x4000>;
> +		#address-cells =3D <1>;
> +		#size-cells =3D <1>;
> +		interrupts =3D <
> +			24 2 0 0
> +			16 2 1 1>;
> +
> +
> +		/* PCIe, DMA, SRIO */
> +		pamu0: pamu@0 {
> +			reg =3D <0 0x1000>;
> +			fsl,primary-cache-geometry =3D <8 1>;
> +			fsl,secondary-cache-geometry =3D <32 2>;
> +		};
> +
> +		/* AXI2, Maple */
> +		pamu1: pamu@1000 {
> +			reg =3D <0x1000 0x1000>;
> +			fsl,primary-cache-geometry =3D <32 1>;
> +			fsl,secondary-cache-geometry =3D <32 2>;
> +		};
> +
> +		/* Q/BMan */
> +		pamu2: pamu@2000 {
> +			reg =3D <0x2000 0x1000>;
> +			fsl,primary-cache-geometry =3D <32 1>;
> +			fsl,secondary-cache-geometry =3D <32 2>;
> +		};
> +
> +		/* AXI1, FMAN */
> +		pamu3: pamu@3000 {
> +			reg =3D <0x3000 0x1000>;
> +			fsl,primary-cache-geometry =3D <32 1>;
> +			fsl,secondary-cache-geometry =3D <32 2>;
> +		};
> +	};
> +
> +/include/ "qoriq-mpic.dtsi"
> +
> +	guts: global-utilities@e0000 {
> +		compatible =3D "fsl,b4-device-config";
> +		reg =3D <0xe0000 0xe00>;
> +		fsl,has-rstcr;
> +		fsl,liodn-bits =3D <12>;
> +	};
> +
> +	rcpm: global-utilities@e2000 {
> +		compatible =3D "fsl,b4-rcpm", "fsl,qoriq-rcpm-2";
> +		reg =3D <0xe2000 0x1000>;
> +	};
> +
> +/include/ "qoriq-dma-0.dtsi"
> +	dma@100300 {
> +		fsl,iommu-parent =3D <&pamu0>;
> +		fsl,liodn-reg =3D <&guts 0x580>; /* DMA1LIODNR */
> +	};
> +
> +/include/ "qoriq-dma-1.dtsi"
> +	dma@101300 {
> +		fsl,iommu-parent =3D <&pamu0>;
> +		fsl,liodn-reg =3D <&guts 0x584>; /* DMA2LIODNR */
> +	};
> +
> +/include/ "qonverge-usb2-dr-0.dtsi"
> +	usb0: usb@210000 {
> +		compatible =3D "fsl-usb2-dr-v2.4", "fsl-usb2-dr";
> +		fsl,iommu-parent =3D <&pamu1>;
> +		fsl,liodn-reg =3D <&guts 0x520>; /* USB1LIODNR */
> +	};
> +
> +/include/ "qoriq-espi-0.dtsi"
> +	spi@110000 {
> +		fsl,espi-num-chipselects =3D <4>;
> +	};
> +
> +/include/ "qoriq-esdhc-0.dtsi"
> +	sdhc@114000 {
> +		sdhci,auto-cmd12;
> +		fsl,iommu-parent =3D <&pamu1>;
> +		fsl,liodn-reg =3D <&guts 0x530>; /* eSDHCLIODNR */
> +	};
> +
> +/include/ "qoriq-i2c-0.dtsi"
> +/include/ "qoriq-i2c-1.dtsi"
> +/include/ "qoriq-duart-0.dtsi"
> +/include/ "qoriq-duart-1.dtsi"
> +/include/ "qoriq-sec5.3-0.dtsi"
> +
> +	L2: l2-cache-controller@c20000 {
> +		compatible =3D "fsl,b4-l2-cache-controller";
> +                reg =3D <0xc20000 0x1000>;

white space issue

> +		next-level-cache =3D <&cpc>;
> +	};
> +};
> diff --git a/arch/powerpc/boot/dts/fsl/b4si-pre.dtsi =
b/arch/powerpc/boot/dts/fsl/b4si-pre.dtsi
> new file mode 100644
> index 0000000..b6161c8
> --- /dev/null
> +++ b/arch/powerpc/boot/dts/fsl/b4si-pre.dtsi
> @@ -0,0 +1,65 @@
> +/*
> + * B4420 Silicon/SoC Device Tree Source (pre include)
> + *
> + * Copyright 2012 Freescale Semiconductor, Inc.
> + *
> + * Redistribution and use in source and binary forms, with or without
> + * modification, are permitted provided that the following conditions =
are met:
> + *     * Redistributions of source code must retain the above =
copyright
> + *       notice, this list of conditions and the following =
disclaimer.
> + *     * Redistributions in binary form must reproduce the above =
copyright
> + *       notice, this list of conditions and the following disclaimer =
in the
> + *       documentation and/or other materials provided with the =
distribution.
> + *     * Neither the name of Freescale Semiconductor nor the
> + *       names of its contributors may be used to endorse or promote =
products
> + *       derived from this software without specific prior written =
permission.
> + *
> + *
> + * ALTERNATIVELY, this software may be distributed under the terms of =
the
> + * GNU General Public License ("GPL") as published by the Free =
Software
> + * Foundation, either version 2 of that License or (at your option) =
any
> + * later version.
> + *
> + * This software is provided by Freescale Semiconductor "as is" and =
any
> + * express or implied warranties, including, but not limited to, the =
implied
> + * warranties of merchantability and fitness for a particular purpose =
are
> + * disclaimed. In no event shall Freescale Semiconductor be liable =
for any
> + * direct, indirect, incidental, special, exemplary, or consequential =
damages
> + * (including, but not limited to, procurement of substitute goods or =
services;
> + * loss of use, data, or profits; or business interruption) however =
caused and
> + * on any theory of liability, whether in contract, strict liability, =
or tort
> + * (including negligence or otherwise) arising in any way out of the =
use of
> + * this software, even if advised of the possibility of such damage.
> + */
> +
> +/ {
> +	compatible =3D "fsl,B4";
> +	#address-cells =3D <2>;
> +	#size-cells =3D <2>;
> +	interrupt-parent =3D <&mpic>;
> +
> +	aliases {
> +		ccsr =3D &soc;
> +		dcsr =3D &dcsr;
> +
> +		serial0 =3D &serial0;
> +		serial1 =3D &serial1;
> +		serial2 =3D &serial2;
> +		serial3 =3D &serial3;
> +		pci0 =3D &pci0;
> +		dma0 =3D &dma0;
> +		dma1 =3D &dma1;
> +		sdhc =3D &sdhc;
> +	};
> +
> +	cpus {
> +		#address-cells =3D <1>;
> +		#size-cells =3D <0>;
> +
> +		cpu0: PowerPC,e6500@0 {
> +			device_type =3D "cpu";
> +			reg =3D <0 1>;
> +			next-level-cache =3D <&L2>;
> +		};
> +	};
> +};
> --=20
> 1.7.6.GIT
>=20

RE: [PATCH 2/5] powerpc/fsl-booke: Add initial silicon device tree files for B4860 and B4420

[Leekha Shaveta-B20052]

-----Original Message-----
From: Kumar Gala [mailto:galak@kernel.crashing.org]=20
Sent: Wednesday, April 03, 2013 10:10 PM
To: Leekha Shaveta-B20052
Cc: linuxppc-dev@lists.ozlabs.org; Zhao Chenhui-B35336; Li Yang-R58472; Tan=
g Yuantian-B29983; Sethi Varun-B16395; Lian Minghuan-B31939; Mehresh Ramnee=
k-B31383; Fleming Andy-AFLEMING; Garg Vakul-B16394
Subject: Re: [PATCH 2/5] powerpc/fsl-booke: Add initial silicon device tree=
 files for B4860 and B4420


On Apr 2, 2013, at 2:16 AM, Shaveta Leekha wrote:

> B4860 and B4420 are similar that share some commonalities
>=20
> * common features have been added in b4si-pre.dtsi and b4si-post.dtsi
> * differences are added in respective silicon files of B4860 and B4420

What are the differences between B4860 & B4420, beyond # of cores?
[SL] have detailed the differences in board support patch sent in this patc=
h set.
Do I need to mention the differences here also?=20

>=20
> There are several things missing from the device trees of B4860 and B4420=
:
>=20
> * DPAA related nodes (Qman, Bman, Fman, Rman)
> * DSP related nodes/information

What about:

serdes, sfp [security fuse processor], thermal, gpio, maple, cpri, quad tim=
ers,=20
[SL] I would prefer to add, what have been added in device tree so far in p=
atch description
As that is clear to me.
But as u suggested, I mentioned some of the nodes/things missing, though th=
e list is not
Exhaustive. Also I am not sure of, what would be added/required in future i=
n these device tree files.

Anyways, I can add all the things you have mentioned above.
Please tell if anything else is missing.

Regards,
Shaveta

>=20
> Signed-off-by: Shaveta Leekha <shaveta@freescale.com>
> Signed-off-by: Zhao Chenhui <chenhui.zhao@freescale.com>
> Signed-off-by: Li Yang <leoli@freescale.com>
> Signed-off-by: Tang Yuantian <Yuantian.Tang@freescale.com>
> Signed-off-by: Varun Sethi <Varun.Sethi@freescale.com>
> Signed-off-by: Minghuan Lian <Minghuan.Lian@freescale.com>
> Signed-off-by: Ramneek Mehresh <ramneek.mehresh@freescale.com>
> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
> Signed-off-by: Andy Fleming <afleming@freescale.com>
> Signed-off-by: Vakul Garg <vakul@freescale.com>
> ---
> arch/powerpc/boot/dts/fsl/b4420si-post.dtsi |   94 ++++++++++
> arch/powerpc/boot/dts/fsl/b4420si-pre.dtsi  |   49 +++++
> arch/powerpc/boot/dts/fsl/b4860si-post.dtsi |  138 ++++++++++++++
> arch/powerpc/boot/dts/fsl/b4860si-pre.dtsi  |   59 ++++++
> arch/powerpc/boot/dts/fsl/b4si-post.dtsi    |  262 ++++++++++++++++++++++=
+++++
> arch/powerpc/boot/dts/fsl/b4si-pre.dtsi     |   65 +++++++

Remove b4si-pre.dtsi, there isn't enough here to warrant not just merging i=
t into b4420si-pre.dtsi & b4860si-pre.dtsi

> 6 files changed, 667 insertions(+), 0 deletions(-) create mode 100644=20
> arch/powerpc/boot/dts/fsl/b4420si-post.dtsi
> create mode 100644 arch/powerpc/boot/dts/fsl/b4420si-pre.dtsi
> create mode 100644 arch/powerpc/boot/dts/fsl/b4860si-post.dtsi
> create mode 100644 arch/powerpc/boot/dts/fsl/b4860si-pre.dtsi
> create mode 100644 arch/powerpc/boot/dts/fsl/b4si-post.dtsi
> create mode 100644 arch/powerpc/boot/dts/fsl/b4si-pre.dtsi
>=20
> diff --git a/arch/powerpc/boot/dts/fsl/b4420si-post.dtsi=20
> b/arch/powerpc/boot/dts/fsl/b4420si-post.dtsi
> new file mode 100644
> index 0000000..bba0c03
> --- /dev/null
> +++ b/arch/powerpc/boot/dts/fsl/b4420si-post.dtsi
> @@ -0,0 +1,94 @@
> +/*
> + * B4420 Silicon/SoC Device Tree Source (post include)
> + *
> + * Copyright 2012 Freescale Semiconductor, Inc.
> + *
> + * Redistribution and use in source and binary forms, with or without
> + * modification, are permitted provided that the following conditions ar=
e met:
> + *     * Redistributions of source code must retain the above copyright
> + *       notice, this list of conditions and the following disclaimer.
> + *     * Redistributions in binary form must reproduce the above copyrig=
ht
> + *       notice, this list of conditions and the following disclaimer in=
 the
> + *       documentation and/or other materials provided with the distribu=
tion.
> + *     * Neither the name of Freescale Semiconductor nor the
> + *       names of its contributors may be used to endorse or promote pro=
ducts
> + *       derived from this software without specific prior written permi=
ssion.
> + *
> + *
> + * ALTERNATIVELY, this software may be distributed under the terms of=20
> +the
> + * GNU General Public License ("GPL") as published by the Free=20
> +Software
> + * Foundation, either version 2 of that License or (at your option)=20
> +any
> + * later version.
> + *
> + * This software is provided by Freescale Semiconductor "as is" and=20
> +any
> + * express or implied warranties, including, but not limited to, the=20
> +implied
> + * warranties of merchantability and fitness for a particular purpose=20
> +are
> + * disclaimed. In no event shall Freescale Semiconductor be liable=20
> +for any
> + * direct, indirect, incidental, special, exemplary, or consequential=20
> +damages
> + * (including, but not limited to, procurement of substitute goods or=20
> +services;
> + * loss of use, data, or profits; or business interruption) however=20
> +caused and
> + * on any theory of liability, whether in contract, strict liability,=20
> +or tort
> + * (including negligence or otherwise) arising in any way out of the=20
> +use of
> + * this software, even if advised of the possibility of such damage.
> + */
> +
> +/include/ "b4si-post.dtsi"
> +
> +/* controller at 0x200000 */
> +&pci0 {
> +	compatible =3D "fsl,b4420-pcie", "fsl,qoriq-pcie-v2.4"; };
> +
> +&dcsr {
> +	dcsr-epu@0 {
> +		compatible =3D "fsl,b4420-dcsr-epu", "fsl,dcsr-epu";
> +	};
> +	dcsr-npc {
> +		compatible =3D "fsl,b4420-dcsr-cnpc", "fsl,dcsr-cnpc";
> +	};
> +	dcsr-dpaa@9000 {
> +		compatible =3D "fsl,b4420-dcsr-dpaa", "fsl,dcsr-dpaa";
> +	};
> +	dcsr-ocn@11000 {
> +		compatible =3D "fsl,b4420-dcsr-ocn", "fsl,dcsr-ocn";
> +	};
> +	dcsr-nal@18000 {
> +		compatible =3D "fsl,b4420-dcsr-nal", "fsl,dcsr-nal";
> +	};
> +	dcsr-rcpm@22000 {
> +		compatible =3D "fsl,b4420-dcsr-rcpm", "fsl,dcsr-rcpm";
> +	};
> +	dcsr-snpc@30000 {
> +		compatible =3D "fsl,b4420-dcsr-snpc", "fsl,dcsr-snpc";
> +	};
> +	dcsr-snpc@31000 {
> +		compatible =3D "fsl,b4420-dcsr-snpc", "fsl,dcsr-snpc";
> +	};
> +	dcsr-cpu-sb-proxy@108000 {
> +		compatible =3D "fsl,dcsr-e6500-sb-proxy", "fsl,dcsr-cpu-sb-proxy";
> +		cpu-handle =3D <&cpu1>;
> +		reg =3D <0x108000 0x1000 0x109000 0x1000>;
> +	};
> +};
> +
> +&soc {
> +	cpc: l3-cache-controller@10000 {
> +		compatible =3D "fsl,b4420-l3-cache-controller", "cache";
> +	};
> +
> +	corenet-cf@18000 {
> +		compatible =3D "fsl,b4420-corenet-cf";
> +	};
> +
> +	guts: global-utilities@e0000 {
> +		compatible =3D "fsl,b4420-device-config", "fsl,qoriq-device-config-2.0=
";
> +	};
> +
> +	clockgen: global-utilities@e1000 {
> +		compatible =3D "fsl,b4420-clockgen", "fsl,qoriq-clockgen-2";
> +	};
> +
> +	L2: l2-cache-controller@c20000 {
> +		compatible =3D "fsl,b4420-l2-cache-controller";
> +	};
> +};
> diff --git a/arch/powerpc/boot/dts/fsl/b4420si-pre.dtsi=20
> b/arch/powerpc/boot/dts/fsl/b4420si-pre.dtsi
> new file mode 100644
> index 0000000..555b0e4
> --- /dev/null
> +++ b/arch/powerpc/boot/dts/fsl/b4420si-pre.dtsi
> @@ -0,0 +1,49 @@
> +/*
> + * B4420 Silicon/SoC Device Tree Source (pre include)
> + *
> + * Copyright 2012 Freescale Semiconductor, Inc.
> + *
> + * Redistribution and use in source and binary forms, with or without
> + * modification, are permitted provided that the following conditions ar=
e met:
> + *     * Redistributions of source code must retain the above copyright
> + *       notice, this list of conditions and the following disclaimer.
> + *     * Redistributions in binary form must reproduce the above copyrig=
ht
> + *       notice, this list of conditions and the following disclaimer in=
 the
> + *       documentation and/or other materials provided with the distribu=
tion.
> + *     * Neither the name of Freescale Semiconductor nor the
> + *       names of its contributors may be used to endorse or promote pro=
ducts
> + *       derived from this software without specific prior written permi=
ssion.
> + *
> + *
> + * ALTERNATIVELY, this software may be distributed under the terms of=20
> +the
> + * GNU General Public License ("GPL") as published by the Free=20
> +Software
> + * Foundation, either version 2 of that License or (at your option)=20
> +any
> + * later version.
> + *
> + * This software is provided by Freescale Semiconductor "as is" and=20
> +any
> + * express or implied warranties, including, but not limited to, the=20
> +implied
> + * warranties of merchantability and fitness for a particular purpose=20
> +are
> + * disclaimed. In no event shall Freescale Semiconductor be liable=20
> +for any
> + * direct, indirect, incidental, special, exemplary, or consequential=20
> +damages
> + * (including, but not limited to, procurement of substitute goods or=20
> +services;
> + * loss of use, data, or profits; or business interruption) however=20
> +caused and
> + * on any theory of liability, whether in contract, strict liability,=20
> +or tort
> + * (including negligence or otherwise) arising in any way out of the=20
> +use of
> + * this software, even if advised of the possibility of such damage.
> + */
> +
> +/dts-v1/;
> +
> +/include/ "b4si-pre.dtsi"
> +
> +/ {
> +	compatible =3D "fsl,B4420";
> +
> +	cpus {
> +		cpu1: PowerPC,e6500@1 {
> +			device_type =3D "cpu";
> +			reg =3D <2 3>;
> +			next-level-cache =3D <&L2>;
> +		};
> +	};
> +};
> diff --git a/arch/powerpc/boot/dts/fsl/b4860si-post.dtsi=20
> b/arch/powerpc/boot/dts/fsl/b4860si-post.dtsi
> new file mode 100644
> index 0000000..f43910f
> --- /dev/null
> +++ b/arch/powerpc/boot/dts/fsl/b4860si-post.dtsi
> @@ -0,0 +1,138 @@
> +/*
> + * B4860 Silicon/SoC Device Tree Source (post include)
> + *
> + * Copyright 2012 Freescale Semiconductor Inc.
> + *
> + * Redistribution and use in source and binary forms, with or without
> + * modification, are permitted provided that the following conditions ar=
e met:
> + *     * Redistributions of source code must retain the above copyright
> + *       notice, this list of conditions and the following disclaimer.
> + *     * Redistributions in binary form must reproduce the above copyrig=
ht
> + *       notice, this list of conditions and the following disclaimer in=
 the
> + *       documentation and/or other materials provided with the distribu=
tion.
> + *     * Neither the name of Freescale Semiconductor nor the
> + *       names of its contributors may be used to endorse or promote pro=
ducts
> + *       derived from this software without specific prior written permi=
ssion.
> + *
> + *
> + * ALTERNATIVELY, this software may be distributed under the terms of=20
> +the
> + * GNU General Public License ("GPL") as published by the Free=20
> +Software
> + * Foundation, either version 2 of that License or (at your option)=20
> +any
> + * later version.
> + *
> + * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND=20
> +ANY
> + * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE=20
> +IMPLIED
> + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE=20
> +ARE
> + * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE=20
> +FOR ANY
> + * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL=20
> +DAMAGES
> + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR=20
> +SERVICES;
> + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER=20
> +CAUSED AND
> + * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,=20
> +OR TORT
> + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE=20
> +USE OF THIS
> + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
> + */
> +
> +/include/ "b4si-post.dtsi"
> +
> +/* controller at 0x200000 */
> +&pci0 {
> +	compatible =3D "fsl,b4860-pcie", "fsl,qoriq-pcie-v2.4"; };
> +
> +&rio {
> +	compatible =3D "fsl,srio";
> +	interrupts =3D <16 2 1 11>;
> +	#address-cells =3D <2>;
> +	#size-cells =3D <2>;
> +	fsl,iommu-parent =3D <&pamu0>;
> +	ranges;
> +
> +	port1 {
> +		#address-cells =3D <2>;
> +		#size-cells =3D <2>;
> +		cell-index =3D <1>;
> +		fsl,liodn-reg =3D <&guts 0x510>; /* RIO1LIODNR */
> +	};
> +
> +	port2 {
> +		#address-cells =3D <2>;
> +		#size-cells =3D <2>;
> +		cell-index =3D <2>;
> +		fsl,liodn-reg =3D <&guts 0x514>; /* RIO2LIODNR */
> +	};
> +};
> +
> +&dcsr {
> +	dcsr-epu@0 {
> +		compatible =3D "fsl,b4860-dcsr-epu", "fsl,dcsr-epu";
> +	};
> +	dcsr-npc {
> +		compatible =3D "fsl,b4860-dcsr-cnpc", "fsl,dcsr-cnpc";
> +	};
> +	dcsr-dpaa@9000 {
> +		compatible =3D "fsl,b4860-dcsr-dpaa", "fsl,dcsr-dpaa";
> +	};
> +	dcsr-ocn@11000 {
> +		compatible =3D "fsl,b4860-dcsr-ocn", "fsl,dcsr-ocn";
> +	};
> +	dcsr-ddr@13000 {
> +		compatible =3D "fsl,dcsr-ddr";
> +		dev-handle =3D <&ddr2>;
> +		reg =3D <0x13000 0x1000>;
> +	};
> +	dcsr-nal@18000 {
> +		compatible =3D "fsl,b4860-dcsr-nal", "fsl,dcsr-nal";
> +	};
> +	dcsr-rcpm@22000 {
> +		compatible =3D "fsl,b4860-dcsr-rcpm", "fsl,dcsr-rcpm";
> +	};
> +	dcsr-snpc@30000 {
> +		compatible =3D "fsl,b4860-dcsr-snpc", "fsl,dcsr-snpc";
> +	};
> +	dcsr-snpc@31000 {
> +		compatible =3D "fsl,b4860-dcsr-snpc", "fsl,dcsr-snpc";
> +	};
> +	dcsr-cpu-sb-proxy@108000 {
> +		compatible =3D "fsl,dcsr-e6500-sb-proxy", "fsl,dcsr-cpu-sb-proxy";
> +		cpu-handle =3D <&cpu1>;
> +		reg =3D <0x108000 0x1000 0x109000 0x1000>;
> +	};
> +	dcsr-cpu-sb-proxy@110000 {
> +		compatible =3D "fsl,dcsr-e6500-sb-proxy", "fsl,dcsr-cpu-sb-proxy";
> +		cpu-handle =3D <&cpu2>;
> +		reg =3D <0x110000 0x1000 0x111000 0x1000>;
> +	};
> +	dcsr-cpu-sb-proxy@118000 {
> +		compatible =3D "fsl,dcsr-e6500-sb-proxy", "fsl,dcsr-cpu-sb-proxy";
> +		cpu-handle =3D <&cpu3>;
> +		reg =3D <0x118000 0x1000 0x119000 0x1000>;
> +	};
> +};
> +
> +&soc {
> +	ddr2: memory-controller@9000 {
> +		compatible =3D "fsl,qoriq-memory-controller-v4.5", "fsl,qoriq-memory-c=
ontroller";
> +		reg =3D <0x9000 0x1000>;
> +		interrupts =3D <16 2 1 9>;
> +	};
> +
> +	cpc: l3-cache-controller@10000 {
> +		compatible =3D "fsl,b4860-l3-cache-controller", "cache";
> +	};
> +
> +	corenet-cf@18000 {
> +		compatible =3D "fsl,b4860-corenet-cf";
> +	};
> +
> +	guts: global-utilities@e0000 {
> +		compatible =3D "fsl,b4860-device-config", "fsl,qoriq-device-config-2.0=
";
> +	};
> +
> +	clockgen: global-utilities@e1000 {
> +		compatible =3D "fsl,b4860-clockgen", "fsl,qoriq-clockgen-2";
> +	};
> +
> +	L2: l2-cache-controller@c20000 {
> +		compatible =3D "fsl,b4860-l2-cache-controller";
> +	};
> +};
> diff --git a/arch/powerpc/boot/dts/fsl/b4860si-pre.dtsi=20
> b/arch/powerpc/boot/dts/fsl/b4860si-pre.dtsi
> new file mode 100644
> index 0000000..f5737a0
> --- /dev/null
> +++ b/arch/powerpc/boot/dts/fsl/b4860si-pre.dtsi
> @@ -0,0 +1,59 @@
> +/*
> + * B4860 Silicon/SoC Device Tree Source (pre include)
> + *
> + * Copyright 2012 Freescale Semiconductor Inc.
> + *
> + * Redistribution and use in source and binary forms, with or without
> + * modification, are permitted provided that the following conditions ar=
e met:
> + *     * Redistributions of source code must retain the above copyright
> + *       notice, this list of conditions and the following disclaimer.
> + *     * Redistributions in binary form must reproduce the above copyrig=
ht
> + *       notice, this list of conditions and the following disclaimer in=
 the
> + *       documentation and/or other materials provided with the distribu=
tion.
> + *     * Neither the name of Freescale Semiconductor nor the
> + *       names of its contributors may be used to endorse or promote pro=
ducts
> + *       derived from this software without specific prior written permi=
ssion.
> + *
> + *
> + * ALTERNATIVELY, this software may be distributed under the terms of=20
> +the
> + * GNU General Public License ("GPL") as published by the Free=20
> +Software
> + * Foundation, either version 2 of that License or (at your option)=20
> +any
> + * later version.
> + *
> + * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND=20
> +ANY
> + * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE=20
> +IMPLIED
> + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE=20
> +ARE
> + * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE=20
> +FOR ANY
> + * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL=20
> +DAMAGES
> + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR=20
> +SERVICES;
> + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER=20
> +CAUSED AND
> + * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,=20
> +OR TORT
> + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE=20
> +USE OF THIS
> + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
> + */
> +
> +/dts-v1/;
> +
> +/include/ "b4si-pre.dtsi"
> +
> +/ {
> +	compatible =3D "fsl,B4860";
> +
> +	cpus {
> +		cpu1: PowerPC,e6500@1 {
> +			device_type =3D "cpu";
> +			reg =3D <2 3>;
> +			next-level-cache =3D <&L2>;
> +		};
> +		cpu2: PowerPC,e6500@2 {
> +			device_type =3D "cpu";
> +			reg =3D <4 5>;
> +			next-level-cache =3D <&L2>;
> +		};
> +		cpu3: PowerPC,e6500@3 {
> +			device_type =3D "cpu";
> +			reg =3D <6 7>;
> +			next-level-cache =3D <&L2>;
> +		};
> +	};
> +};
> diff --git a/arch/powerpc/boot/dts/fsl/b4si-post.dtsi=20
> b/arch/powerpc/boot/dts/fsl/b4si-post.dtsi
> new file mode 100644
> index 0000000..06c97a2
> --- /dev/null
> +++ b/arch/powerpc/boot/dts/fsl/b4si-post.dtsi
> @@ -0,0 +1,262 @@
> +/*
> + * B4420 Silicon/SoC Device Tree Source (post include)
> + *
> + * Copyright 2012 Freescale Semiconductor, Inc.
> + *
> + * Redistribution and use in source and binary forms, with or without
> + * modification, are permitted provided that the following conditions ar=
e met:
> + *     * Redistributions of source code must retain the above copyright
> + *       notice, this list of conditions and the following disclaimer.
> + *     * Redistributions in binary form must reproduce the above copyrig=
ht
> + *       notice, this list of conditions and the following disclaimer in=
 the
> + *       documentation and/or other materials provided with the distribu=
tion.
> + *     * Neither the name of Freescale Semiconductor nor the
> + *       names of its contributors may be used to endorse or promote pro=
ducts
> + *       derived from this software without specific prior written permi=
ssion.
> + *
> + *
> + * ALTERNATIVELY, this software may be distributed under the terms of=20
> +the
> + * GNU General Public License ("GPL") as published by the Free=20
> +Software
> + * Foundation, either version 2 of that License or (at your option)=20
> +any
> + * later version.
> + *
> + * This software is provided by Freescale Semiconductor "as is" and=20
> +any
> + * express or implied warranties, including, but not limited to, the=20
> +implied
> + * warranties of merchantability and fitness for a particular purpose=20
> +are
> + * disclaimed. In no event shall Freescale Semiconductor be liable=20
> +for any
> + * direct, indirect, incidental, special, exemplary, or consequential=20
> +damages
> + * (including, but not limited to, procurement of substitute goods or=20
> +services;
> + * loss of use, data, or profits; or business interruption) however=20
> +caused and
> + * on any theory of liability, whether in contract, strict liability,=20
> +or tort
> + * (including negligence or otherwise) arising in any way out of the=20
> +use of
> + * this software, even if advised of the possibility of such damage.
> + */
> +
> +&ifc {
> +	#address-cells =3D <2>;
> +	#size-cells =3D <1>;
> +	compatible =3D "fsl,ifc", "simple-bus";
> +	interrupts =3D <25 2 0 0>;
> +};
> +
> +/* controller at 0x200000 */
> +&pci0 {
> +	compatible =3D "fsl,b4-pcie", "fsl,qoriq-pcie-v2.4";
> +	device_type =3D "pci";
> +	#size-cells =3D <2>;
> +	#address-cells =3D <3>;
> +	bus-range =3D <0x0 0xff>;
> +	interrupts =3D <20 2 0 0>;
> +	fsl,iommu-parent =3D <&pamu0>;
> +	pcie@0 {
> +		#interrupt-cells =3D <1>;
> +		#size-cells =3D <2>;
> +		#address-cells =3D <3>;
> +		device_type =3D "pci";
> +		interrupts =3D <20 2 0 0>;
> +		interrupt-map-mask =3D <0xf800 0 0 7>;
> +		interrupt-map =3D <
> +			/* IDSEL 0x0 */
> +			0000 0 0 1 &mpic 40 1 0 0
> +			0000 0 0 2 &mpic 1 1 0 0
> +			0000 0 0 3 &mpic 2 1 0 0
> +			0000 0 0 4 &mpic 3 1 0 0
> +			>;
> +	};
> +};
> +
> +&dcsr {
> +	#address-cells =3D <1>;
> +	#size-cells =3D <1>;
> +	compatible =3D "fsl,dcsr", "simple-bus";
> +
> +	dcsr-epu@0 {
> +		compatible =3D "fsl,b4-dcsr-epu", "fsl,dcsr-epu";
> +		interrupts =3D <52 2 0 0
> +			      84 2 0 0
> +			      85 2 0 0
> +			      94 2 0 0
> +			      95 2 0 0>;
> +		reg =3D <0x0 0x1000>;
> +	};
> +	dcsr-npc {
> +		compatible =3D "fsl,b4-dcsr-cnpc", "fsl,dcsr-cnpc";
> +		reg =3D <0x1000 0x1000 0x1002000 0x10000>;
> +	};
> +	dcsr-nxc@2000 {
> +		compatible =3D "fsl,dcsr-nxc";
> +		reg =3D <0x2000 0x1000>;
> +	};
> +	dcsr-corenet {
> +		compatible =3D "fsl,dcsr-corenet";
> +		reg =3D <0x8000 0x1000 0x1A000 0x1000>;
> +	};
> +	dcsr-dpaa@9000 {
> +		compatible =3D "fsl,b4-dcsr-dpaa", "fsl,dcsr-dpaa";
> +		reg =3D <0x9000 0x1000>;
> +	};
> +	dcsr-ocn@11000 {
> +		compatible =3D "fsl,b4-dcsr-ocn", "fsl,dcsr-ocn";
> +		reg =3D <0x11000 0x1000>;
> +	};
> +	dcsr-ddr@12000 {
> +		compatible =3D "fsl,dcsr-ddr";
> +		dev-handle =3D <&ddr1>;
> +		reg =3D <0x12000 0x1000>;
> +	};
> +	dcsr-nal@18000 {
> +		compatible =3D "fsl,b4-dcsr-nal", "fsl,dcsr-nal";
> +		reg =3D <0x18000 0x1000>;
> +	};
> +	dcsr-rcpm@22000 {
> +		compatible =3D "fsl,b4-dcsr-rcpm", "fsl,dcsr-rcpm";
> +		reg =3D <0x22000 0x1000>;
> +	};
> +	dcsr-snpc@30000 {
> +		compatible =3D "fsl,b4-dcsr-snpc", "fsl,dcsr-snpc";
> +		reg =3D <0x30000 0x1000 0x1022000 0x10000>;
> +	};
> +	dcsr-snpc@31000 {
> +		compatible =3D "fsl,b4-dcsr-snpc", "fsl,dcsr-snpc";
> +		reg =3D <0x31000 0x1000 0x1042000 0x10000>;
> +	};
> +	dcsr-cpu-sb-proxy@100000 {
> +		compatible =3D "fsl,dcsr-e6500-sb-proxy", "fsl,dcsr-cpu-sb-proxy";
> +		cpu-handle =3D <&cpu0>;
> +		reg =3D <0x100000 0x1000 0x101000 0x1000>;
> +	};
> +};
> +
> +&soc {
> +	#address-cells =3D <1>;
> +	#size-cells =3D <1>;
> +	device_type =3D "soc";
> +	compatible =3D "simple-bus";
> +
> +	soc-sram-error {
> +		compatible =3D "fsl,soc-sram-error";
> +		interrupts =3D <16 2 1 2>;
> +	};
> +
> +	corenet-law@0 {
> +		compatible =3D "fsl,corenet-law";
> +		reg =3D <0x0 0x1000>;
> +		fsl,num-laws =3D <32>;
> +	};
> +
> +	ddr1: memory-controller@8000 {
> +		compatible =3D "fsl,qoriq-memory-controller-v4.5", "fsl,qoriq-memory-c=
ontroller";
> +		reg =3D <0x8000 0x1000>;
> +		interrupts =3D <16 2 1 8>;
> +	};
> +
> +	cpc: l3-cache-controller@10000 {
> +		compatible =3D "fsl,b4-l3-cache-controller", "cache";
> +		reg =3D <0x10000 0x1000>;
> +		interrupts =3D <16 2 1 4>;
> +	};
> +
> +	corenet-cf@18000 {
> +		compatible =3D "fsl,b4-corenet-cf";
> +		reg =3D <0x18000 0x1000>;
> +		interrupts =3D <16 2 1 0>;
> +		fsl,ccf-num-csdids =3D <32>;
> +		fsl,ccf-num-snoopids =3D <32>;
> +	};
> +
> +	iommu@20000 {
> +		compatible =3D  "fsl,pamu-v1.0", "fsl,pamu";
> +		reg =3D <0x20000 0x4000>;
> +		#address-cells =3D <1>;
> +		#size-cells =3D <1>;
> +		interrupts =3D <
> +			24 2 0 0
> +			16 2 1 1>;
> +
> +
> +		/* PCIe, DMA, SRIO */
> +		pamu0: pamu@0 {
> +			reg =3D <0 0x1000>;
> +			fsl,primary-cache-geometry =3D <8 1>;
> +			fsl,secondary-cache-geometry =3D <32 2>;
> +		};
> +
> +		/* AXI2, Maple */
> +		pamu1: pamu@1000 {
> +			reg =3D <0x1000 0x1000>;
> +			fsl,primary-cache-geometry =3D <32 1>;
> +			fsl,secondary-cache-geometry =3D <32 2>;
> +		};
> +
> +		/* Q/BMan */
> +		pamu2: pamu@2000 {
> +			reg =3D <0x2000 0x1000>;
> +			fsl,primary-cache-geometry =3D <32 1>;
> +			fsl,secondary-cache-geometry =3D <32 2>;
> +		};
> +
> +		/* AXI1, FMAN */
> +		pamu3: pamu@3000 {
> +			reg =3D <0x3000 0x1000>;
> +			fsl,primary-cache-geometry =3D <32 1>;
> +			fsl,secondary-cache-geometry =3D <32 2>;
> +		};
> +	};
> +
> +/include/ "qoriq-mpic.dtsi"
> +
> +	guts: global-utilities@e0000 {
> +		compatible =3D "fsl,b4-device-config";
> +		reg =3D <0xe0000 0xe00>;
> +		fsl,has-rstcr;
> +		fsl,liodn-bits =3D <12>;
> +	};
> +
> +	rcpm: global-utilities@e2000 {
> +		compatible =3D "fsl,b4-rcpm", "fsl,qoriq-rcpm-2";
> +		reg =3D <0xe2000 0x1000>;
> +	};
> +
> +/include/ "qoriq-dma-0.dtsi"
> +	dma@100300 {
> +		fsl,iommu-parent =3D <&pamu0>;
> +		fsl,liodn-reg =3D <&guts 0x580>; /* DMA1LIODNR */
> +	};
> +
> +/include/ "qoriq-dma-1.dtsi"
> +	dma@101300 {
> +		fsl,iommu-parent =3D <&pamu0>;
> +		fsl,liodn-reg =3D <&guts 0x584>; /* DMA2LIODNR */
> +	};
> +
> +/include/ "qonverge-usb2-dr-0.dtsi"
> +	usb0: usb@210000 {
> +		compatible =3D "fsl-usb2-dr-v2.4", "fsl-usb2-dr";
> +		fsl,iommu-parent =3D <&pamu1>;
> +		fsl,liodn-reg =3D <&guts 0x520>; /* USB1LIODNR */
> +	};
> +
> +/include/ "qoriq-espi-0.dtsi"
> +	spi@110000 {
> +		fsl,espi-num-chipselects =3D <4>;
> +	};
> +
> +/include/ "qoriq-esdhc-0.dtsi"
> +	sdhc@114000 {
> +		sdhci,auto-cmd12;
> +		fsl,iommu-parent =3D <&pamu1>;
> +		fsl,liodn-reg =3D <&guts 0x530>; /* eSDHCLIODNR */
> +	};
> +
> +/include/ "qoriq-i2c-0.dtsi"
> +/include/ "qoriq-i2c-1.dtsi"
> +/include/ "qoriq-duart-0.dtsi"
> +/include/ "qoriq-duart-1.dtsi"
> +/include/ "qoriq-sec5.3-0.dtsi"
> +
> +	L2: l2-cache-controller@c20000 {
> +		compatible =3D "fsl,b4-l2-cache-controller";
> +                reg =3D <0xc20000 0x1000>;

white space issue

> +		next-level-cache =3D <&cpc>;
> +	};
> +};
> diff --git a/arch/powerpc/boot/dts/fsl/b4si-pre.dtsi=20
> b/arch/powerpc/boot/dts/fsl/b4si-pre.dtsi
> new file mode 100644
> index 0000000..b6161c8
> --- /dev/null
> +++ b/arch/powerpc/boot/dts/fsl/b4si-pre.dtsi
> @@ -0,0 +1,65 @@
> +/*
> + * B4420 Silicon/SoC Device Tree Source (pre include)
> + *
> + * Copyright 2012 Freescale Semiconductor, Inc.
> + *
> + * Redistribution and use in source and binary forms, with or without
> + * modification, are permitted provided that the following conditions ar=
e met:
> + *     * Redistributions of source code must retain the above copyright
> + *       notice, this list of conditions and the following disclaimer.
> + *     * Redistributions in binary form must reproduce the above copyrig=
ht
> + *       notice, this list of conditions and the following disclaimer in=
 the
> + *       documentation and/or other materials provided with the distribu=
tion.
> + *     * Neither the name of Freescale Semiconductor nor the
> + *       names of its contributors may be used to endorse or promote pro=
ducts
> + *       derived from this software without specific prior written permi=
ssion.
> + *
> + *
> + * ALTERNATIVELY, this software may be distributed under the terms of=20
> +the
> + * GNU General Public License ("GPL") as published by the Free=20
> +Software
> + * Foundation, either version 2 of that License or (at your option)=20
> +any
> + * later version.
> + *
> + * This software is provided by Freescale Semiconductor "as is" and=20
> +any
> + * express or implied warranties, including, but not limited to, the=20
> +implied
> + * warranties of merchantability and fitness for a particular purpose=20
> +are
> + * disclaimed. In no event shall Freescale Semiconductor be liable=20
> +for any
> + * direct, indirect, incidental, special, exemplary, or consequential=20
> +damages
> + * (including, but not limited to, procurement of substitute goods or=20
> +services;
> + * loss of use, data, or profits; or business interruption) however=20
> +caused and
> + * on any theory of liability, whether in contract, strict liability,=20
> +or tort
> + * (including negligence or otherwise) arising in any way out of the=20
> +use of
> + * this software, even if advised of the possibility of such damage.
> + */
> +
> +/ {
> +	compatible =3D "fsl,B4";
> +	#address-cells =3D <2>;
> +	#size-cells =3D <2>;
> +	interrupt-parent =3D <&mpic>;
> +
> +	aliases {
> +		ccsr =3D &soc;
> +		dcsr =3D &dcsr;
> +
> +		serial0 =3D &serial0;
> +		serial1 =3D &serial1;
> +		serial2 =3D &serial2;
> +		serial3 =3D &serial3;
> +		pci0 =3D &pci0;
> +		dma0 =3D &dma0;
> +		dma1 =3D &dma1;
> +		sdhc =3D &sdhc;
> +	};
> +
> +	cpus {
> +		#address-cells =3D <1>;
> +		#size-cells =3D <0>;
> +
> +		cpu0: PowerPC,e6500@0 {
> +			device_type =3D "cpu";
> +			reg =3D <0 1>;
> +			next-level-cache =3D <&L2>;
> +		};
> +	};
> +};
> --
> 1.7.6.GIT
>=20

Re: [PATCH 2/5] powerpc/fsl-booke: Add initial silicon device tree files for B4860 and B4420

[Kumar Gala]

On Apr 4, 2013, at 2:10 AM, Leekha Shaveta-B20052 wrote:

>=20
>=20
> -----Original Message-----
> From: Kumar Gala [mailto:galak@kernel.crashing.org]=20
> Sent: Wednesday, April 03, 2013 10:10 PM
> To: Leekha Shaveta-B20052
> Cc: linuxppc-dev@lists.ozlabs.org; Zhao Chenhui-B35336; Li =
Yang-R58472; Tang Yuantian-B29983; Sethi Varun-B16395; Lian =
Minghuan-B31939; Mehresh Ramneek-B31383; Fleming Andy-AFLEMING; Garg =
Vakul-B16394
> Subject: Re: [PATCH 2/5] powerpc/fsl-booke: Add initial silicon device =
tree files for B4860 and B4420
>=20
>=20
> On Apr 2, 2013, at 2:16 AM, Shaveta Leekha wrote:
>=20
>> B4860 and B4420 are similar that share some commonalities
>>=20
>> * common features have been added in b4si-pre.dtsi and b4si-post.dtsi
>> * differences are added in respective silicon files of B4860 and =
B4420
>=20
> What are the differences between B4860 & B4420, beyond # of cores?
> [SL] have detailed the differences in board support patch sent in this =
patch set.
> Do I need to mention the differences here also?=20
>=20
>>=20
>> There are several things missing from the device trees of B4860 and =
B4420:
>>=20
>> * DPAA related nodes (Qman, Bman, Fman, Rman)
>> * DSP related nodes/information
>=20
> What about:
>=20
> serdes, sfp [security fuse processor], thermal, gpio, maple, cpri, =
quad timers,=20
> [SL] I would prefer to add, what have been added in device tree so far =
in patch description
> As that is clear to me.
> But as u suggested, I mentioned some of the nodes/things missing, =
though the list is not
> Exhaustive. Also I am not sure of, what would be added/required in =
future in these device tree files.
>=20
> Anyways, I can add all the things you have mentioned above.
> Please tell if anything else is missing.

I would add the trivial ones and just make sure the list is exhaustive =
for the ones missing in the commit message.

>=20
> Regards,
> Shaveta
>=20
>>=20
>> Signed-off-by: Shaveta Leekha <shaveta@freescale.com>
>> Signed-off-by: Zhao Chenhui <chenhui.zhao@freescale.com>
>> Signed-off-by: Li Yang <leoli@freescale.com>
>> Signed-off-by: Tang Yuantian <Yuantian.Tang@freescale.com>
>> Signed-off-by: Varun Sethi <Varun.Sethi@freescale.com>
>> Signed-off-by: Minghuan Lian <Minghuan.Lian@freescale.com>
>> Signed-off-by: Ramneek Mehresh <ramneek.mehresh@freescale.com>
>> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
>> Signed-off-by: Andy Fleming <afleming@freescale.com>
>> Signed-off-by: Vakul Garg <vakul@freescale.com>
>> ---
>> arch/powerpc/boot/dts/fsl/b4420si-post.dtsi |   94 ++++++++++
>> arch/powerpc/boot/dts/fsl/b4420si-pre.dtsi  |   49 +++++
>> arch/powerpc/boot/dts/fsl/b4860si-post.dtsi |  138 ++++++++++++++
>> arch/powerpc/boot/dts/fsl/b4860si-pre.dtsi  |   59 ++++++
>> arch/powerpc/boot/dts/fsl/b4si-post.dtsi    |  262 =
+++++++++++++++++++++++++++
>> arch/powerpc/boot/dts/fsl/b4si-pre.dtsi     |   65 +++++++
>=20
> Remove b4si-pre.dtsi, there isn't enough here to warrant not just =
merging it into b4420si-pre.dtsi & b4860si-pre.dtsi
>=20

- k

RE: [PATCH 2/5] powerpc/fsl-booke: Add initial silicon device tree files for B4860 and B4420

[Leekha Shaveta-B20052]

-----Original Message-----
From: Kumar Gala [mailto:galak@kernel.crashing.org]=20
Sent: Friday, April 05, 2013 12:44 AM
To: Leekha Shaveta-B20052
Cc: linuxppc-dev@lists.ozlabs.org; Zhao Chenhui-B35336; Li Yang-R58472; Tan=
g Yuantian-B29983; Sethi Varun-B16395; Lian Minghuan-B31939; Mehresh Ramnee=
k-B31383; Fleming Andy-AFLEMING; Garg Vakul-B16394
Subject: Re: [PATCH 2/5] powerpc/fsl-booke: Add initial silicon device tree=
 files for B4860 and B4420


On Apr 4, 2013, at 2:10 AM, Leekha Shaveta-B20052 wrote:

>=20
>=20
> -----Original Message-----
> From: Kumar Gala [mailto:galak@kernel.crashing.org]
> Sent: Wednesday, April 03, 2013 10:10 PM
> To: Leekha Shaveta-B20052
> Cc: linuxppc-dev@lists.ozlabs.org; Zhao Chenhui-B35336; Li=20
> Yang-R58472; Tang Yuantian-B29983; Sethi Varun-B16395; Lian=20
> Minghuan-B31939; Mehresh Ramneek-B31383; Fleming Andy-AFLEMING; Garg=20
> Vakul-B16394
> Subject: Re: [PATCH 2/5] powerpc/fsl-booke: Add initial silicon device=20
> tree files for B4860 and B4420
>=20
>=20
> On Apr 2, 2013, at 2:16 AM, Shaveta Leekha wrote:
>=20
>> B4860 and B4420 are similar that share some commonalities
>>=20
>> * common features have been added in b4si-pre.dtsi and b4si-post.dtsi
>> * differences are added in respective silicon files of B4860 and=20
>> B4420
>=20
> What are the differences between B4860 & B4420, beyond # of cores?
> [SL] have detailed the differences in board support patch sent in this pa=
tch set.
> Do I need to mention the differences here also?=20
>=20
>>=20
>> There are several things missing from the device trees of B4860 and B442=
0:
>>=20
>> * DPAA related nodes (Qman, Bman, Fman, Rman)
>> * DSP related nodes/information
>=20
> What about:
>=20
> serdes, sfp [security fuse processor], thermal, gpio, maple, cpri,=20
> quad timers, [SL] I would prefer to add, what have been added in=20
> device tree so far in patch description As that is clear to me.
> But as u suggested, I mentioned some of the nodes/things missing,=20
> though the list is not Exhaustive. Also I am not sure of, what would be a=
dded/required in future in these device tree files.
>=20
> Anyways, I can add all the things you have mentioned above.
> Please tell if anything else is missing.

I would add the trivial ones and just make sure the list is exhaustive for =
the ones missing in the commit message.
[SL] Adding " serdes, sfp [security fuse processor], thermal, gpio, maple, =
cpri, quad timers as missing things"
in my commit message. If I still miss some, Please add while applying the p=
atch.

Thanks,
Shaveta

>=20
> Regards,
> Shaveta
>=20
>>=20
>> Signed-off-by: Shaveta Leekha <shaveta@freescale.com>
>> Signed-off-by: Zhao Chenhui <chenhui.zhao@freescale.com>
>> Signed-off-by: Li Yang <leoli@freescale.com>
>> Signed-off-by: Tang Yuantian <Yuantian.Tang@freescale.com>
>> Signed-off-by: Varun Sethi <Varun.Sethi@freescale.com>
>> Signed-off-by: Minghuan Lian <Minghuan.Lian@freescale.com>
>> Signed-off-by: Ramneek Mehresh <ramneek.mehresh@freescale.com>
>> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
>> Signed-off-by: Andy Fleming <afleming@freescale.com>
>> Signed-off-by: Vakul Garg <vakul@freescale.com>
>> ---
>> arch/powerpc/boot/dts/fsl/b4420si-post.dtsi |   94 ++++++++++
>> arch/powerpc/boot/dts/fsl/b4420si-pre.dtsi  |   49 +++++
>> arch/powerpc/boot/dts/fsl/b4860si-post.dtsi |  138 ++++++++++++++
>> arch/powerpc/boot/dts/fsl/b4860si-pre.dtsi  |   59 ++++++
>> arch/powerpc/boot/dts/fsl/b4si-post.dtsi    |  262 +++++++++++++++++++++=
++++++
>> arch/powerpc/boot/dts/fsl/b4si-pre.dtsi     |   65 +++++++
>=20
> Remove b4si-pre.dtsi, there isn't enough here to warrant not just=20
> merging it into b4420si-pre.dtsi & b4860si-pre.dtsi
>=20

- k