From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from e33.co.us.ibm.com (e33.co.us.ibm.com [32.97.110.151]) (using TLSv1 with cipher DHE-RSA-AES256-SHA (256/256 bits)) (Client CN "e33.co.us.ibm.com", Issuer "GeoTrust SSL CA" (not verified)) by ozlabs.org (Postfix) with ESMTPS id 803F22C0143 for ; Wed, 24 Apr 2013 19:37:56 +1000 (EST) Received: from /spool/local by e33.co.us.ibm.com with IBM ESMTP SMTP Gateway: Authorized Use Only! Violators will be prosecuted for from ; Wed, 24 Apr 2013 03:37:53 -0600 Received: from d03relay02.boulder.ibm.com (d03relay02.boulder.ibm.com [9.17.195.227]) by d03dlp01.boulder.ibm.com (Postfix) with ESMTP id CB7FD1FF0039 for ; Wed, 24 Apr 2013 03:32:41 -0600 (MDT) Received: from d03av04.boulder.ibm.com (d03av04.boulder.ibm.com [9.17.195.170]) by d03relay02.boulder.ibm.com (8.13.8/8.13.8/NCO v10.0) with ESMTP id r3O9bi0o121594 for ; Wed, 24 Apr 2013 03:37:44 -0600 Received: from d03av04.boulder.ibm.com (loopback [127.0.0.1]) by d03av04.boulder.ibm.com (8.14.4/8.13.1/NCO v10.0 AVout) with ESMTP id r3O9bhZ2004573 for ; Wed, 24 Apr 2013 03:37:44 -0600 From: Gavin Shan To: linuxppc-dev@lists.ozlabs.org Subject: [PATCH v3 0/7] powerpc/powernv: PHB3 Support Date: Wed, 24 Apr 2013 17:37:32 +0800 Message-Id: <1366796259-29412-1-git-send-email-shangw@linux.vnet.ibm.com> Cc: Gavin Shan List-Id: Linux on PowerPC Developers Mail List List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , The patchset includes minimal support for PHB3. Initially, flag "PNV_PHB_IODA2" is introduced to differentiate IODA2 compliant PHB3 from other types of PHBs and do initialization accordingly for PHB3. Besides, variable IODA2 tables reside in system memory and we allocate them in kernel, then pass them to f/w and enable the corresponding BARs through OPAL API. The P/Q bits of IVE should be handled on PHB3 by software and the patchset intends to cover that as well. NOTE: The first patch comes from Ben. v2 -> v3 * Remove the unnecessary quirk. That's only useful with simics * Do MSI EOI in single OPAL API opal_pci_msi_eoi() * Use explicit branch to fully utilize CPU's prefetching engine while doing TCE invalidation * Add one patch to fix invalid IOMMU table for PCI devices v1 -> v2 * Introduce CONFIG_POWERNV_MSI, which is similiar to CONFIG_PSERIES_MSI * Enable CONFIG_PPC_MSI_BITMAP while selecting CONFIG_POWERNV_MSI * Eleminate (struct pnv_phb::msi_count) since it has been removed in linux-next * Replace (CONFIG_PPC_POWERNV && CONFIG_PCI_MSI) with CONFIG_POWERNV_MSI * Move declaration of pnv_pci_msi_eoi() to asm/xics.h * Remove unnecessary "#ifdef ... #endif" in icp-native.c * Add support to invalidate TCE * Let the IODA2 table allocated by firmware and kernel to retrieve them through device-tree --- arch/powerpc/include/asm/iommu.h | 1 + arch/powerpc/include/asm/opal.h | 7 +- arch/powerpc/include/asm/xics.h | 3 + arch/powerpc/platforms/powernv/Kconfig | 5 + arch/powerpc/platforms/powernv/opal-wrappers.S | 1 + arch/powerpc/platforms/powernv/pci-ioda.c | 301 ++++++++++++++++++++---- arch/powerpc/platforms/powernv/pci-p5ioc2.c | 1 + arch/powerpc/platforms/powernv/pci.c | 85 +++---- arch/powerpc/platforms/powernv/pci.h | 28 ++- arch/powerpc/sysdev/Kconfig | 1 + arch/powerpc/sysdev/xics/icp-native.c | 27 ++- 11 files changed, 356 insertions(+), 104 deletions(-) Thanks, Gavin