From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from e7.ny.us.ibm.com (e7.ny.us.ibm.com [32.97.182.137]) (using TLSv1 with cipher DHE-RSA-AES256-SHA (256/256 bits)) (Client CN "e7.ny.us.ibm.com", Issuer "GeoTrust SSL CA" (not verified)) by ozlabs.org (Postfix) with ESMTPS id 2DDB52C00F5 for ; Wed, 15 May 2013 13:35:25 +1000 (EST) Received: from /spool/local by e7.ny.us.ibm.com with IBM ESMTP SMTP Gateway: Authorized Use Only! Violators will be prosecuted for from ; Tue, 14 May 2013 23:35:23 -0400 Received: from d01relay04.pok.ibm.com (d01relay04.pok.ibm.com [9.56.227.236]) by d01dlp01.pok.ibm.com (Postfix) with ESMTP id A6B0C38C804D for ; Tue, 14 May 2013 23:35:19 -0400 (EDT) Received: from d01av03.pok.ibm.com (d01av03.pok.ibm.com [9.56.224.217]) by d01relay04.pok.ibm.com (8.13.8/8.13.8/NCO v10.0) with ESMTP id r4F3ZJVF315150 for ; Tue, 14 May 2013 23:35:20 -0400 Received: from d01av03.pok.ibm.com (loopback [127.0.0.1]) by d01av03.pok.ibm.com (8.14.4/8.13.1/NCO v10.0 AVout) with ESMTP id r4F3ZHvv006918 for ; Wed, 15 May 2013 00:35:19 -0300 From: Gavin Shan To: linuxppc-dev@lists.ozlabs.org Subject: [PATCH 20/22] powerpc/eeh: Enable EEH check for config access Date: Wed, 15 May 2013 11:34:56 +0800 Message-Id: <1368588898-16224-21-git-send-email-shangw@linux.vnet.ibm.com> In-Reply-To: <1368588898-16224-1-git-send-email-shangw@linux.vnet.ibm.com> References: <1368588898-16224-1-git-send-email-shangw@linux.vnet.ibm.com> Cc: Gavin Shan List-Id: Linux on PowerPC Developers Mail List List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , The patch enables EEH check and let EEH core to process the EEH errors for PowerNV platform while accessing config space. Originally, the implementation already had mechanism to check EEH errors and tried to recover from them. However, we never let EEH core to handle the EEH errors. Signed-off-by: Gavin Shan --- arch/powerpc/platforms/powernv/pci.c | 41 +++++++++++++++++++++++++++++++++- 1 files changed, 40 insertions(+), 1 deletions(-) diff --git a/arch/powerpc/platforms/powernv/pci.c b/arch/powerpc/platforms/powernv/pci.c index 55dfca844..15144e4 100644 --- a/arch/powerpc/platforms/powernv/pci.c +++ b/arch/powerpc/platforms/powernv/pci.c @@ -32,6 +32,8 @@ #include #include #include +#include +#include #include "powernv.h" #include "pci.h" @@ -254,6 +256,10 @@ static int pnv_pci_read_config(struct pci_bus *bus, { struct pci_controller *hose = pci_bus_to_host(bus); struct pnv_phb *phb = hose->private_data; +#ifdef CONFIG_EEH + struct device_node *busdn, *dn; + struct eeh_pe *phb_pe = NULL; +#endif u32 bdfn = (((uint64_t)bus->number) << 8) | devfn; s64 rc; @@ -286,8 +292,35 @@ static int pnv_pci_read_config(struct pci_bus *bus, cfg_dbg("pnv_pci_read_config bus: %x devfn: %x +%x/%x -> %08x\n", bus->number, devfn, where, size, *val); - /* Check if the PHB got frozen due to an error (no response) */ + /* + * Check if the specified PE has been put into frozen + * state. On the other hand, we needn't do that while + * the PHB has been put into frozen state because of + * PHB-fatal errors. + */ +#ifdef CONFIG_EEH + phb_pe = eeh_phb_pe_get(hose); + if (phb_pe && (phb_pe->state & EEH_PE_ISOLATED)) + return PCIBIOS_SUCCESSFUL; + + if (phb->eeh_enabled) { + if (*val == EEH_IO_ERROR_VALUE(size)) { + busdn = pci_bus_to_OF_node(bus); + for (dn = busdn->child; dn; dn = dn->sibling) { + struct pci_dn *pdn = PCI_DN(dn); + + if (pdn && pdn->devfn == devfn && + eeh_dev_check_failure(of_node_to_eeh_dev(dn), + EEH_EVENT_NORMAL)) + return PCIBIOS_DEVICE_NOT_FOUND; + } + } + } else { + pnv_pci_config_check_eeh(phb, bus, bdfn); + } +#else pnv_pci_config_check_eeh(phb, bus, bdfn); +#endif return PCIBIOS_SUCCESSFUL; } @@ -318,8 +351,14 @@ static int pnv_pci_write_config(struct pci_bus *bus, default: return PCIBIOS_FUNC_NOT_SUPPORTED; } + /* Check if the PHB got frozen due to an error (no response) */ +#ifdef CONFIG_EEH + if (!phb->eeh_enabled) + pnv_pci_config_check_eeh(phb, bus, bdfn); +#else pnv_pci_config_check_eeh(phb, bus, bdfn); +#endif return PCIBIOS_SUCCESSFUL; } -- 1.7.5.4