Re: [PATCH 3/5] powerpc/dts: update MSI bindings doc for MPIC v4.3

[Scott Wood <scottwood@freescale.com>]

On 06/17/2013 09:49:19 PM, Lian Minghuan-b31939 wrote:
> On 06/18/2013 08:42 AM, Scott Wood wrote:
>> On 06/17/2013 07:28:07 PM, Scott Wood wrote:
>>> On 06/17/2013 12:07:41 AM, Lian Minghuan-b31939 wrote:
>>>>>> +    compatible =3D "fsl,mpic-msi";
>>>>>> +    reg =3D <0x41600 0x200 0x44140 4>;
>>>>>=20
>>>>> Why 0x200?
>>>>>=20
>>>> [Minghuan] The offsets of the MSIA registers are from 0x41600 to =20
>>>> 0x417ff, and the size is 0x200.
>>>> offset 0x41600-0x4170 are MSIIRA1-7.
>>>> 0x41720 is MSISRA,
>>>> 0x41750 is MSIIR.
>>>> The others are reserved.
>>>=20
>>> There is no MSIIRA on fsl,mpic-msi.
>>=20
>> Sigh, I was thinking of MSIIR1A -- which of course is distinct from =20
>> both MSIIRA1 and MSIIRA. :-P
>>=20
>> So it's just a bug that pq3-mpic.dtsi has a length of 0x80?
> [Minghuan] I am sorry, there is a typo.
> offset 0x41600-0x4170 should be MSIRA0-7.
> The MSI bank size is 0x200.
> The MSIR 0-7 size is 0x80.
> So the first region of 'reg' should indicate bank size or MSIR size?
> I think it should be a bank size. So MSI driver can access MSISR and =20
> MSIIR, and provide some new features in feature.

It should be the bank size.  There's already inconsistency between =20
pq3-mpic.dtsi and qoriq-mpic.dtsi (the latter has 0x200).  I think =20
pq3-mpic.dtsi is just wrong and should be fixed.

-Scott=