[PATCH 1/2] [PATCH] powerpc/85xx: add P1020RDB-PD platform support

[PATCH 1/2] [PATCH] powerpc/85xx: add P1020RDB-PD platform support

[Haijun Zhang]

From: "Haijun.Zhang" <Haijun.Zhang@freescale.com>

The p1020rdb-pd has the similar feature as the p1020rdb.
Therefore, p1020rdb-pd use the same platform file as the p1/p2 rdb board.
Overview of P1020RDB-PD platform:
- DDR3 2GB
- NOR flash 64MB
- NAND flash 128MB
- SPI flash 16MB
- I2C EEPROM 256Kb
	- eTSEC1 (RGMII PHY) connected to VSC7385 L2 switch
	- eTSEC2 (SGMII PHY)
- eTSEC3 (RGMII PHY)
	- SDHC
	- 2 USB ports
	- 4 TDM ports
	- PCIe

Signed-off-by: Haijun Zhang <Haijun.Zhang@freescale.com>
Signed-off-by: Jerry Huang <Chang-Ming.Huang@freescale.com>
CC: Scott Wood <scottwood@freescale.com>
---
 arch/powerpc/platforms/85xx/mpc85xx_rdb.c | 22 ++++++++++++++++++++++
 1 file changed, 22 insertions(+)

diff --git a/arch/powerpc/platforms/85xx/mpc85xx_rdb.c b/arch/powerpc/platforms/85xx/mpc85xx_rdb.c
index ede8771..53b6fb0 100644
--- a/arch/powerpc/platforms/85xx/mpc85xx_rdb.c
+++ b/arch/powerpc/platforms/85xx/mpc85xx_rdb.c
@@ -160,6 +160,7 @@ machine_arch_initcall(p2020_rdb_pc, mpc85xx_common_publish_devices);
 machine_arch_initcall(p1020_mbg_pc, mpc85xx_common_publish_devices);
 machine_arch_initcall(p1020_rdb, mpc85xx_common_publish_devices);
 machine_arch_initcall(p1020_rdb_pc, mpc85xx_common_publish_devices);
+machine_arch_initcall(p1020_rdb_pd, mpc85xx_common_publish_devices);
 machine_arch_initcall(p1020_utm_pc, mpc85xx_common_publish_devices);
 machine_arch_initcall(p1021_rdb_pc, mpc85xx_common_publish_devices);
 machine_arch_initcall(p1025_rdb, mpc85xx_common_publish_devices);
@@ -193,6 +194,13 @@ static int __init p1020_rdb_pc_probe(void)
 	return of_flat_dt_is_compatible(root, "fsl,P1020RDB-PC");
 }
 
+static int __init p1020_rdb_pd_probe(void)
+{
+	unsigned long root = of_get_flat_dt_root();
+
+	return of_flat_dt_is_compatible(root, "fsl,P1020RDB-PD");
+}
+
 static int __init p1021_rdb_pc_probe(void)
 {
 	unsigned long root = of_get_flat_dt_root();
@@ -351,6 +359,20 @@ define_machine(p1020_rdb_pc) {
 	.progress		= udbg_progress,
 };
 
+define_machine(p1020_rdb_pd) {
+	.name			= "P1020RDB-PD",
+	.probe			= p1020_rdb_pd_probe,
+	.setup_arch		= mpc85xx_rdb_setup_arch,
+	.init_IRQ		= mpc85xx_rdb_pic_init,
+#ifdef CONFIG_PCI
+	.pcibios_fixup_bus	= fsl_pcibios_fixup_bus,
+#endif
+	.get_irq		= mpic_get_irq,
+	.restart		= fsl_rstcr_restart,
+	.calibrate_decr		= generic_calibrate_decr,
+	.progress		= udbg_progress,
+};
+
 define_machine(p1024_rdb) {
 	.name			= "P1024 RDB",
 	.probe			= p1024_rdb_probe,
-- 
1.8.0

[PATCH 2/2] powerpc/85xx: add the P1020RDB-PD DTS support

[Haijun Zhang]

From: "Haijun.Zhang" <Haijun.Zhang@freescale.com>

Overview of P1020RDB-PD device:
- DDR3 2GB
- NOR flash 64MB
- NAND flash 128MB
- SPI flash 16MB
- I2C EEPROM 256Kb
- eTSEC1 (RGMII PHY) connected to VSC7385 L2 switch
- eTSEC2 (SGMII PHY)
- eTSEC3 (RGMII PHY)
- SDHC
- 2 USB ports
- 4 TDM ports
- PCIe

Signed-off-by: Haijun Zhang <Haijun.Zhang@freescale.com>
Signed-off-by: Jerry Huang <Chang-Ming.Huang@freescale.com>
CC: Scott Wood <scottwood@freescale.com>
---
 arch/powerpc/boot/dts/p1020rdb-pd.dtsi    | 257 ++++++++++++++++++++++++++++++
 arch/powerpc/boot/dts/p1020rdb-pd_32b.dts |  90 +++++++++++
 2 files changed, 347 insertions(+)
 create mode 100644 arch/powerpc/boot/dts/p1020rdb-pd.dtsi
 create mode 100644 arch/powerpc/boot/dts/p1020rdb-pd_32b.dts

diff --git a/arch/powerpc/boot/dts/p1020rdb-pd.dtsi b/arch/powerpc/boot/dts/p1020rdb-pd.dtsi
new file mode 100644
index 0000000..6e07fa7
--- /dev/null
+++ b/arch/powerpc/boot/dts/p1020rdb-pd.dtsi
@@ -0,0 +1,257 @@
+/*
+ * P1020RDB-PD Device Tree Source stub (no addresses or top-level ranges)
+ *
+ * Copyright 2013 Freescale Semiconductor Inc.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *     * Redistributions of source code must retain the above copyright
+ *       notice, this list of conditions and the following disclaimer.
+ *     * Redistributions in binary form must reproduce the above copyright
+ *       notice, this list of conditions and the following disclaimer in the
+ *       documentation and/or other materials provided with the distribution.
+ *     * Neither the name of Freescale Semiconductor nor the
+ *       names of its contributors may be used to endorse or promote products
+ *       derived from this software without specific prior written permission.
+ *
+ *
+ * ALTERNATIVELY, this software may be distributed under the terms of the
+ * GNU General Public License ("GPL") as published by the Free Software
+ * Foundation, either version 2 of that License or (at your option) any
+ * later version.
+ *
+ * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY
+ * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+&lbc {
+	nor@0,0 {
+		#address-cells = <1>;
+		#size-cells = <1>;
+		compatible = "cfi-flash";
+		reg = <0x0 0x0 0x4000000>;
+		bank-width = <2>;
+		device-width = <1>;
+
+		partition@0 {
+			/* 128KB for DTB Image */
+			reg = <0x0 0x00020000>;
+			label = "NOR DTB Image";
+		};
+
+		partition@20000 {
+			/* 3.875 MB for Linux Kernel Image */
+			reg = <0x00020000 0x003e0000>;
+			label = "NOR Linux Kernel Image";
+		};
+
+		partition@400000 {
+			/* 58MB for Root file System */
+			reg = <0x00400000 0x03a00000>;
+			label = "NOR Root File System";
+		};
+
+		partition@3e00000 {
+			/* This location must not be altered  */
+			/* 1M for Vitesse 7385 Switch firmware */
+			reg = <0x3e00000 0x00100000>;
+			label = "NOR Vitesse-7385 Firmware";
+			read-only;
+		};
+
+		partition@3f00000 {
+			/* This location must not be altered  */
+			/* 512KB for u-boot Bootloader Image */
+			/* 512KB for u-boot Environment Variables */
+			reg = <0x03f00000 0x00100000>;
+			label = "NOR U-Boot Image";
+			read-only;
+		};
+	};
+
+	nand@1,0 {
+		#address-cells = <1>;
+		#size-cells = <1>;
+		compatible = "fsl,p1020-fcm-nand",
+			     "fsl,elbc-fcm-nand";
+		reg = <0x1 0x0 0x40000>;
+
+		partition@0 {
+			/* This location must not be altered  */
+			/* 1MB for u-boot Bootloader Image */
+			reg = <0x0 0x00100000>;
+			label = "NAND U-Boot Image";
+			read-only;
+		};
+
+		partition@100000 {
+			/* 1MB for DTB Image */
+			reg = <0x00100000 0x00100000>;
+			label = "NAND DTB Image";
+		};
+
+		partition@200000 {
+			/* 4MB for Linux Kernel Image */
+			reg = <0x00200000 0x00400000>;
+			label = "NAND Linux Kernel Image";
+		};
+
+		partition@600000 {
+			/* 4MB for Compressed Root file System Image */
+			reg = <0x00600000 0x00400000>;
+			label = "NAND Compressed RFS Image";
+		};
+
+		partition@a00000 {
+			/* 22MB for JFFS2 based Root file System */
+			reg = <0x00a00000 0x01600000>;
+			label = "NAND JFFS2 Root File System";
+		};
+
+		partition@2000000 {
+			/* 96MB for RAMDISK based Root file System */
+			reg = <0x02000000 0x06000000>;
+			label = "NAND Writable User area";
+		};
+	};
+
+	cpld@2,0 {
+		#address-cells = <1>;
+		#size-cells = <1>;
+		compatible = "cpld";
+		reg = <0x2 0x0 0x20000>;
+		read-only;
+	};
+
+	L2switch@3,0 {
+		#address-cells = <1>;
+		#size-cells = <1>;
+		compatible = "vitesse-7385";
+		reg = <0x3 0x0 0x20000>;
+	};
+};
+
+&soc {
+	i2c@3000 {
+		rtc@68 {
+			compatible = "dallas,ds1339";
+			reg = <0x68>;
+		};
+	};
+
+	spi@7000 {
+		flash@0 {
+			#address-cells = <1>;
+			#size-cells = <1>;
+			compatible = "spansion,s25sl12801";
+			reg = <0>;
+			spi-max-frequency = <40000000>; /* input clock */
+
+			partition@u-boot {
+				/* 512KB for u-boot Bootloader Image */
+				reg = <0x0 0x00080000>;
+				label = "u-boot";
+				read-only;
+			};
+
+			partition@dtb {
+				/* 512KB for DTB Image*/
+				reg = <0x00080000 0x00080000>;
+				label = "dtb";
+			};
+
+			partition@kernel {
+				/* 4MB for Linux Kernel Image */
+				reg = <0x00100000 0x00400000>;
+				label = "kernel";
+			};
+
+			partition@fs {
+				/* 4MB for Compressed RFS Image */
+				reg = <0x00500000 0x00400000>;
+				label = "file system";
+			};
+
+			partition@jffs-fs {
+				/* 7MB for JFFS2 based RFS */
+				reg = <0x00900000 0x00700000>;
+				label = "file system jffs2";
+			};
+		};
+		slic@0 {
+			compatible = "zarlink,le88266";
+			reg = <1>;
+			spi-max-frequency = <8000000>;
+		};
+		slic@1 {
+			compatible = "zarlink,le88266";
+			reg = <2>;
+			spi-max-frequency = <8000000>;
+		};
+
+	};
+
+	mdio@24000 {
+		phy0: ethernet-phy@0 {
+			interrupts = <3 1 0 0>;
+			reg = <0x0>;
+		};
+		phy1: ethernet-phy@1 {
+			interrupts = <2 1 0 0>;
+			reg = <0x1>;
+		};
+	};
+
+	mdio@25000 {
+		tbi1: tbi-phy@11 {
+			reg = <0x11>;
+			device_type = "tbi-phy";
+		};
+	};
+
+	mdio@26000 {
+		tbi2: tbi-phy@11 {
+			reg = <0x11>;
+			device_type = "tbi-phy";
+		};
+	};
+
+	enet0: ethernet@b0000 {
+		fixed-link = <1 1 1000 0 0>;
+		phy-connection-type = "rgmii-id";
+	};
+
+	enet1: ethernet@b1000 {
+		phy-handle = <&phy0>;
+		tbi-handle = <&tbi1>;
+		phy-connection-type = "sgmii";
+	};
+
+	enet2: ethernet@b2000 {
+		phy-handle = <&phy1>;
+		phy-connection-type = "rgmii-id";
+	};
+
+	usb@22000 {
+		phy_type = "ulpi";
+	};
+
+	/* USB2 is shared with localbus, so it must be disabled
+	   by default. We can't put 'status = "disabled";' here
+	   since U-Boot doesn't clear the status property when
+	   it enables USB2. OTOH, U-Boot does create a new node
+	   when there isn't any. So, just comment it out.
+	*/
+	usb@23000 {
+		status = "disabled";
+		phy_type = "ulpi";
+	};
+};
diff --git a/arch/powerpc/boot/dts/p1020rdb-pd_32b.dts b/arch/powerpc/boot/dts/p1020rdb-pd_32b.dts
new file mode 100644
index 0000000..160702b
--- /dev/null
+++ b/arch/powerpc/boot/dts/p1020rdb-pd_32b.dts
@@ -0,0 +1,90 @@
+/*
+ * P1020 RDB-PD Device Tree Source (32-bit address map)
+ *
+ * Copyright 2013 Freescale Semiconductor Inc.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *     * Redistributions of source code must retain the above copyright
+ *       notice, this list of conditions and the following disclaimer.
+ *     * Redistributions in binary form must reproduce the above copyright
+ *       notice, this list of conditions and the following disclaimer in the
+ *       documentation and/or other materials provided with the distribution.
+ *     * Neither the name of Freescale Semiconductor nor the
+ *       names of its contributors may be used to endorse or promote products
+ *       derived from this software without specific prior written permission.
+ *
+ *
+ * ALTERNATIVELY, this software may be distributed under the terms of the
+ * GNU General Public License ("GPL") as published by the Free Software
+ * Foundation, either version 2 of that License or (at your option) any
+ * later version.
+ *
+ * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY
+ * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+/include/ "fsl/p1020si-pre.dtsi"
+/ {
+	model = "fsl,P1020RDB-PD";
+	compatible = "fsl,P1020RDB-PD";
+
+	memory {
+		device_type = "memory";
+	};
+
+	lbc: localbus@ffe05000 {
+		reg = <0x0 0xffe05000 0x0 0x1000>;
+
+		/* NOR, NAND flash and L2 switch */
+		ranges = <0x0 0x0 0x0 0xec000000 0x04000000
+			  0x1 0x0 0x0 0xff800000 0x00040000
+			  0x2 0x0 0x0 0xffa00000 0x00020000
+			  0x3 0x0 0x0 0xffb00000 0x00020000>;
+	};
+
+	soc: soc@ffe00000 {
+		ranges = <0x0 0x0 0xffe00000 0x100000>;
+	};
+
+	pci0: pcie@ffe09000 {
+		reg = <0x0 0xffe09000 0x0 0x1000>;
+		ranges = <0x2000000 0x0 0xa0000000 0x0 0xa0000000 0x0 0x20000000
+			  0x1000000 0x0 0x00000000 0x0 0xffc10000 0x0 0x10000>;
+		pcie@0 {
+			ranges = <0x2000000 0x0 0xa0000000
+				  0x2000000 0x0 0xa0000000
+				  0x0 0x20000000
+
+				  0x1000000 0x0 0x0
+				  0x1000000 0x0 0x0
+				  0x0 0x100000>;
+		};
+	};
+
+	pci1: pcie@ffe0a000 {
+		reg = <0x0 0xffe0a000 0x0 0x1000>;
+		ranges = <0x2000000 0x0 0x80000000 0x0 0x80000000 0x0 0x20000000
+			  0x1000000 0x0 0x00000000 0x0 0xffc00000 0x0 0x10000>;
+		pcie@0 {
+			ranges = <0x2000000 0x0 0x80000000
+				  0x2000000 0x0 0x80000000
+				  0x0 0x20000000
+
+				  0x1000000 0x0 0x0
+				  0x1000000 0x0 0x0
+				  0x0 0x100000>;
+		};
+	};
+};
+
+/include/ "p1020rdb-pd.dtsi"
+/include/ "fsl/p1020si-post.dtsi"
-- 
1.8.0

Re: [PATCH 2/2] powerpc/85xx: add the P1020RDB-PD DTS support

[Scott Wood]

On 06/30/2013 11:12:23 PM, Haijun Zhang wrote:
> From: "Haijun.Zhang" <Haijun.Zhang@freescale.com>
>=20
> Overview of P1020RDB-PD device:
> - DDR3 2GB
> - NOR flash 64MB
> - NAND flash 128MB
> - SPI flash 16MB
> - I2C EEPROM 256Kb
> - eTSEC1 (RGMII PHY) connected to VSC7385 L2 switch
> - eTSEC2 (SGMII PHY)
> - eTSEC3 (RGMII PHY)
> - SDHC
> - 2 USB ports
> - 4 TDM ports
> - PCIe
>=20
> Signed-off-by: Haijun Zhang <Haijun.Zhang@freescale.com>
> Signed-off-by: Jerry Huang <Chang-Ming.Huang@freescale.com>
> CC: Scott Wood <scottwood@freescale.com>
> ---
>  arch/powerpc/boot/dts/p1020rdb-pd.dtsi    | 257 =20
> ++++++++++++++++++++++++++++++
>  arch/powerpc/boot/dts/p1020rdb-pd_32b.dts |  90 +++++++++++
>  2 files changed, 347 insertions(+)
>  create mode 100644 arch/powerpc/boot/dts/p1020rdb-pd.dtsi
>  create mode 100644 arch/powerpc/boot/dts/p1020rdb-pd_32b.dts

What about 36b?

> +	cpld@2,0 {
> +		#address-cells =3D <1>;
> +		#size-cells =3D <1>;
> +		compatible =3D "cpld";
> +		reg =3D <0x2 0x0 0x20000>;
> +		read-only;
> +	};

Where does "cpld" as a compatible come from (it's way too vague)?  What =20
is read-only supposed to mean here?

Why do you have #address-cells/#size-cells if there are no child nodes?

-Scott=

答复: [PATCH 2/2] powerpc/85xx: add the P1020RDB-PD DTS support

[Zhang Haijun-B42677]

CgpSZWdhcmRzICYgVGhhbmtzCgpIYWlqdW4uCgpfX19fX19fX19fX19fX19fX19fX19fX19fX19f
X19fX19fX19fX19fCreivP7IyzogV29vZCBTY290dC1CMDc0MjEKt6LLzcqxvOQ6IDIwMTPE6jfU
wjPI1SAxOTowOQrK1bz+yMs6IFpoYW5nIEhhaWp1bi1CNDI2NzcKQ2M6IGdhbGFrQGtlcm5lbC5j
cmFzaGluZy5vcmc7IGxpbnV4cHBjLWRldkBsaXN0cy5vemxhYnMub3JnOyBaaGFuZyBIYWlqdW4t
QjQyNjc3OyBIdWFuZyBDaGFuZ21pbmctUjY2MDkzCtb3zOI6IFJlOiBbUEFUQ0ggMi8yXSBwb3dl
cnBjLzg1eHg6IGFkZCB0aGUgUDEwMjBSREItUEQgRFRTIHN1cHBvcnQKCk9uIDA2LzMwLzIwMTMg
MTE6MTI6MjMgUE0sIEhhaWp1biBaaGFuZyB3cm90ZToKPiBGcm9tOiAiSGFpanVuLlpoYW5nIiA8
SGFpanVuLlpoYW5nQGZyZWVzY2FsZS5jb20+Cj4KPiBPdmVydmlldyBvZiBQMTAyMFJEQi1QRCBk
ZXZpY2U6Cj4gLSBERFIzIDJHQgo+IC0gTk9SIGZsYXNoIDY0TUIKPiAtIE5BTkQgZmxhc2ggMTI4
TUIKPiAtIFNQSSBmbGFzaCAxNk1CCj4gLSBJMkMgRUVQUk9NIDI1NktiCj4gLSBlVFNFQzEgKFJH
TUlJIFBIWSkgY29ubmVjdGVkIHRvIFZTQzczODUgTDIgc3dpdGNoCj4gLSBlVFNFQzIgKFNHTUlJ
IFBIWSkKPiAtIGVUU0VDMyAoUkdNSUkgUEhZKQo+IC0gU0RIQwo+IC0gMiBVU0IgcG9ydHMKPiAt
IDQgVERNIHBvcnRzCj4gLSBQQ0llCj4KPiBTaWduZWQtb2ZmLWJ5OiBIYWlqdW4gWmhhbmcgPEhh
aWp1bi5aaGFuZ0BmcmVlc2NhbGUuY29tPgo+IFNpZ25lZC1vZmYtYnk6IEplcnJ5IEh1YW5nIDxD
aGFuZy1NaW5nLkh1YW5nQGZyZWVzY2FsZS5jb20+Cj4gQ0M6IFNjb3R0IFdvb2QgPHNjb3R0d29v
ZEBmcmVlc2NhbGUuY29tPgo+IC0tLQo+ICBhcmNoL3Bvd2VycGMvYm9vdC9kdHMvcDEwMjByZGIt
cGQuZHRzaSAgICB8IDI1Nwo+ICsrKysrKysrKysrKysrKysrKysrKysrKysrKysrKwo+ICBhcmNo
L3Bvd2VycGMvYm9vdC9kdHMvcDEwMjByZGItcGRfMzJiLmR0cyB8ICA5MCArKysrKysrKysrKwo+
ICAyIGZpbGVzIGNoYW5nZWQsIDM0NyBpbnNlcnRpb25zKCspCj4gIGNyZWF0ZSBtb2RlIDEwMDY0
NCBhcmNoL3Bvd2VycGMvYm9vdC9kdHMvcDEwMjByZGItcGQuZHRzaQo+ICBjcmVhdGUgbW9kZSAx
MDA2NDQgYXJjaC9wb3dlcnBjL2Jvb3QvZHRzL3AxMDIwcmRiLXBkXzMyYi5kdHMKCldoYXQgYWJv
dXQgMzZiPwoKSGFpanVuOiAyRyBERFIgd2FzIGZpeCBvbiBQMTAyMFJEQi1QRCBib2FyZC4gTm8g
bmVlZCAzNmJpdCBzdXBwb3J0LiBBbHNvIG5vIDM2Yml0IHVib290IHN1cHBvcnQuCgoKPiArICAg
ICBjcGxkQDIsMCB7Cj4gKyAgICAgICAgICAgICAjYWRkcmVzcy1jZWxscyA9IDwxPjsKPiArICAg
ICAgICAgICAgICNzaXplLWNlbGxzID0gPDE+Owo+ICsgICAgICAgICAgICAgY29tcGF0aWJsZSA9
ICJjcGxkIjsKPiArICAgICAgICAgICAgIHJlZyA9IDwweDIgMHgwIDB4MjAwMDA+Owo+ICsgICAg
ICAgICAgICAgcmVhZC1vbmx5Owo+ICsgICAgIH07CgpXaGVyZSBkb2VzICJjcGxkIiBhcyBhIGNv
bXBhdGlibGUgY29tZSBmcm9tIChpdCdzIHdheSB0b28gdmFndWUpPyAgV2hhdAppcyByZWFkLW9u
bHkgc3VwcG9zZWQgdG8gbWVhbiBoZXJlPwoKSGFpanVuOiBJbiBmYWN0IGFsbW9zdCBhbGwgYm9h
cmQgaGFzIGl0cyBzcGVjaWFsIENQTEQuIFRoaXMgbm9kZSBqdXN0IGNvcHkgZnJvbSBwMTAyMHJk
Yi1wYyBib2FyZC4KClNvLCBjaGFuZ2UgaXQgdG8gOgoKY3BsZEAyLDAgewogICAgICAgICAgY29t
cGF0aWJsZSA9ICJmc2wsIHAxMDIwcmRiLWNwbGQiOwogICAgICAgICAgcmVnID0gPDB4MiAweDAg
MHgyMDAwMD47CiAgICAgICAgICByZWFkLW9ubHk7Cn07CgpDUExEIHdhcyBqdXN0IGxpa2UgYSBF
RVBST00sIGl0IGNvbnRhaW4gdGhlIGNvbmZpZyBpbmZvcm1hdGlvbiBhYm91dCBURE0sIExFRCwg
UE9XRVIsIHdhdGNoZG9nLCBGWE8sIEZYUyBhbmQgc28gb24uCldlIGNoYW5nZWQgaXQgdW5kZXIg
dWJvb3QsIHdoZW4ga2VybmVsIHNldHVwIHdlIG9ubHkgbmVlZCB0byByZWFkLCBzdXBwb3NlZCBu
b3QgYmUgY2hhbmdlZC4KCldoeSBkbyB5b3UgaGF2ZSAjYWRkcmVzcy1jZWxscy8jc2l6ZS1jZWxs
cyBpZiB0aGVyZSBhcmUgbm8gY2hpbGQgbm9kZXM/CgpJJ2xsIHJlbW92ZSB0aGlzLgoKCi1TY290
dAo=

Re: 答复: [PATCH 2/2] powerpc/85xx: add the P1020RDB-PD DTS support

[Scott Wood]

On 07/03/2013 09:04:40 PM, Zhang Haijun-B42677 wrote:
>=20
>=20
> Regards & Thanks
>=20
> Haijun.
>=20
> ________________________________________
> =E5=8F=91=E4=BB=B6=E4=BA=BA: Wood Scott-B07421
> =E5=8F=91=E9=80=81=E6=97=B6=E9=97=B4: 2013=E5=B9=B47=E6=9C=883=E6=97=A5 1=
9:09
> =E6=94=B6=E4=BB=B6=E4=BA=BA: Zhang Haijun-B42677
> Cc: galak@kernel.crashing.org; linuxppc-dev@lists.ozlabs.org; Zhang =20
> Haijun-B42677; Huang Changming-R66093
> =E4=B8=BB=E9=A2=98: Re: [PATCH 2/2] powerpc/85xx: add the P1020RDB-PD DTS=
 support
>=20
> On 06/30/2013 11:12:23 PM, Haijun Zhang wrote:
> > From: "Haijun.Zhang" <Haijun.Zhang@freescale.com>
> >
> > Overview of P1020RDB-PD device:
> > - DDR3 2GB
> > - NOR flash 64MB
> > - NAND flash 128MB
> > - SPI flash 16MB
> > - I2C EEPROM 256Kb
> > - eTSEC1 (RGMII PHY) connected to VSC7385 L2 switch
> > - eTSEC2 (SGMII PHY)
> > - eTSEC3 (RGMII PHY)
> > - SDHC
> > - 2 USB ports
> > - 4 TDM ports
> > - PCIe
> >
> > Signed-off-by: Haijun Zhang <Haijun.Zhang@freescale.com>
> > Signed-off-by: Jerry Huang <Chang-Ming.Huang@freescale.com>
> > CC: Scott Wood <scottwood@freescale.com>
> > ---
> >  arch/powerpc/boot/dts/p1020rdb-pd.dtsi    | 257
> > ++++++++++++++++++++++++++++++
> >  arch/powerpc/boot/dts/p1020rdb-pd_32b.dts |  90 +++++++++++
> >  2 files changed, 347 insertions(+)
> >  create mode 100644 arch/powerpc/boot/dts/p1020rdb-pd.dtsi
> >  create mode 100644 arch/powerpc/boot/dts/p1020rdb-pd_32b.dts
>=20
> What about 36b?
>=20
> Haijun: 2G DDR was fix on P1020RDB-PD board. No need 36bit support. =20
> Also no 36bit uboot support.

So then why not just have one "p1020rdb-pd.dts"?

Or, can you have a common p1020rdb.dtsi that all the variants use, with =20
the .dts file only handling the differences?

> > +     cpld@2,0 {
> > +             #address-cells =3D <1>;
> > +             #size-cells =3D <1>;
> > +             compatible =3D "cpld";
> > +             reg =3D <0x2 0x0 0x20000>;
> > +             read-only;
> > +     };
>=20
> Where does "cpld" as a compatible come from (it's way too vague)?  =20
> What
> is read-only supposed to mean here?
>=20
> Haijun: In fact almost all board has its special CPLD. This node just =20
> copy from p1020rdb-pc board.
>=20
> So, change it to :
>=20
> cpld@2,0 {
>           compatible =3D "fsl, p1020rdb-cpld";
>           reg =3D <0x2 0x0 0x20000>;
>           read-only;
> };

Again, what is read-only supposed to mean here?  I don't care that it's =20
copied from the PC version.  It doesn't make sense, and is not =20
documented in a binding.

Is the -pd CPLD 100% identical to the -pc CPLD?  If not, shouldn't the =20
compatible note the difference between the two?

-Scott=

答复: 答复: [PATCH 2/2] powerpc/85xx: add the P1020RDB-PD DTS support

[Zhang Haijun-B42677]

CgpSZWdhcmRzICYgVGhhbmtzCgpIYWlqdW4uCgpfX19fX19fX19fX19fX19fX19fX19fX19fX19f
X19fX19fX19fX19fCreivP7IyzogV29vZCBTY290dC1CMDc0MjEKt6LLzcqxvOQ6IDIwMTPE6jfU
wjjI1SAxNzowOArK1bz+yMs6IFpoYW5nIEhhaWp1bi1CNDI2NzcKs63LzTogV29vZCBTY290dC1C
MDc0MjE7IGdhbGFrQGtlcm5lbC5jcmFzaGluZy5vcmc7IGxpbnV4cHBjLWRldkBsaXN0cy5vemxh
YnMub3JnOyBIdWFuZyBDaGFuZ21pbmctUjY2MDkzOyBYaWUgWGlhb2JvLVI2MzA2MQrW98ziOiBS
ZTogtPC4tDogW1BBVENIIDIvMl0gcG93ZXJwYy84NXh4OiBhZGQgdGhlIFAxMDIwUkRCLVBEIERU
UyBzdXBwb3J0CgpPbiAwNy8wMy8yMDEzIDA5OjA0OjQwIFBNLCBaaGFuZyBIYWlqdW4tQjQyNjc3
IHdyb3RlOgo+Cj4KPiBSZWdhcmRzICYgVGhhbmtzCj4KPiBIYWlqdW4uCj4KPiBfX19fX19fX19f
X19fX19fX19fX19fX19fX19fX19fX19fX19fX19fCj4gt6K8/sjLOiBXb29kIFNjb3R0LUIwNzQy
MQo+ILeiy83KsbzkOiAyMDEzxOo31MIzyNUgMTk6MDkKPiDK1bz+yMs6IFpoYW5nIEhhaWp1bi1C
NDI2NzcKPiBDYzogZ2FsYWtAa2VybmVsLmNyYXNoaW5nLm9yZzsgbGludXhwcGMtZGV2QGxpc3Rz
Lm96bGFicy5vcmc7IFpoYW5nCj4gSGFpanVuLUI0MjY3NzsgSHVhbmcgQ2hhbmdtaW5nLVI2NjA5
Mwo+INb3zOI6IFJlOiBbUEFUQ0ggMi8yXSBwb3dlcnBjLzg1eHg6IGFkZCB0aGUgUDEwMjBSREIt
UEQgRFRTIHN1cHBvcnQKPgo+IE9uIDA2LzMwLzIwMTMgMTE6MTI6MjMgUE0sIEhhaWp1biBaaGFu
ZyB3cm90ZToKPiA+IEZyb206ICJIYWlqdW4uWmhhbmciIDxIYWlqdW4uWmhhbmdAZnJlZXNjYWxl
LmNvbT4KPiA+Cj4gPiBPdmVydmlldyBvZiBQMTAyMFJEQi1QRCBkZXZpY2U6Cj4gPiAtIEREUjMg
MkdCCj4gPiAtIE5PUiBmbGFzaCA2NE1CCj4gPiAtIE5BTkQgZmxhc2ggMTI4TUIKPiA+IC0gU1BJ
IGZsYXNoIDE2TUIKPiA+IC0gSTJDIEVFUFJPTSAyNTZLYgo+ID4gLSBlVFNFQzEgKFJHTUlJIFBI
WSkgY29ubmVjdGVkIHRvIFZTQzczODUgTDIgc3dpdGNoCj4gPiAtIGVUU0VDMiAoU0dNSUkgUEhZ
KQo+ID4gLSBlVFNFQzMgKFJHTUlJIFBIWSkKPiA+IC0gU0RIQwo+ID4gLSAyIFVTQiBwb3J0cwo+
ID4gLSA0IFRETSBwb3J0cwo+ID4gLSBQQ0llCj4gPgo+ID4gU2lnbmVkLW9mZi1ieTogSGFpanVu
IFpoYW5nIDxIYWlqdW4uWmhhbmdAZnJlZXNjYWxlLmNvbT4KPiA+IFNpZ25lZC1vZmYtYnk6IEpl
cnJ5IEh1YW5nIDxDaGFuZy1NaW5nLkh1YW5nQGZyZWVzY2FsZS5jb20+Cj4gPiBDQzogU2NvdHQg
V29vZCA8c2NvdHR3b29kQGZyZWVzY2FsZS5jb20+Cj4gPiAtLS0KPiA+ICBhcmNoL3Bvd2VycGMv
Ym9vdC9kdHMvcDEwMjByZGItcGQuZHRzaSAgICB8IDI1Nwo+ID4gKysrKysrKysrKysrKysrKysr
KysrKysrKysrKysrCj4gPiAgYXJjaC9wb3dlcnBjL2Jvb3QvZHRzL3AxMDIwcmRiLXBkXzMyYi5k
dHMgfCAgOTAgKysrKysrKysrKysKPiA+ICAyIGZpbGVzIGNoYW5nZWQsIDM0NyBpbnNlcnRpb25z
KCspCj4gPiAgY3JlYXRlIG1vZGUgMTAwNjQ0IGFyY2gvcG93ZXJwYy9ib290L2R0cy9wMTAyMHJk
Yi1wZC5kdHNpCj4gPiAgY3JlYXRlIG1vZGUgMTAwNjQ0IGFyY2gvcG93ZXJwYy9ib290L2R0cy9w
MTAyMHJkYi1wZF8zMmIuZHRzCj4KPiBXaGF0IGFib3V0IDM2Yj8KPgo+IEhhaWp1bjogMkcgRERS
IHdhcyBmaXggb24gUDEwMjBSREItUEQgYm9hcmQuIE5vIG5lZWQgMzZiaXQgc3VwcG9ydC4KPiBB
bHNvIG5vIDM2Yml0IHVib290IHN1cHBvcnQuCgpTbyB0aGVuIHdoeSBub3QganVzdCBoYXZlIG9u
ZSAicDEwMjByZGItcGQuZHRzIj8KCk9ro6wgaSdsbCByZW1vdmUgJ18zMmInLgoKT3IsIGNhbiB5
b3UgaGF2ZSBhIGNvbW1vbiBwMTAyMHJkYi5kdHNpIHRoYXQgYWxsIHRoZSB2YXJpYW50cyB1c2Us
IHdpdGgKdGhlIC5kdHMgZmlsZSBvbmx5IGhhbmRsaW5nIHRoZSBkaWZmZXJlbmNlcz8KCkkgdGhp
bmsgbm8gbmVlZCB0byBkbyB0aGlzLCBhbG1vc3QgYWxsIG9mIHZhcmlhbnRzIGluIHh4eC5kdHNp
IGFyZSBkaWZmZXJlbnQuIAoKPiA+ICsgICAgIGNwbGRAMiwwIHsKPiA+ICsgICAgICAgICAgICAg
I2FkZHJlc3MtY2VsbHMgPSA8MT47Cj4gPiArICAgICAgICAgICAgICNzaXplLWNlbGxzID0gPDE+
Owo+ID4gKyAgICAgICAgICAgICBjb21wYXRpYmxlID0gImNwbGQiOwo+ID4gKyAgICAgICAgICAg
ICByZWcgPSA8MHgyIDB4MCAweDIwMDAwPjsKPiA+ICsgICAgICAgICAgICAgcmVhZC1vbmx5Owo+
ID4gKyAgICAgfTsKPgo+IFdoZXJlIGRvZXMgImNwbGQiIGFzIGEgY29tcGF0aWJsZSBjb21lIGZy
b20gKGl0J3Mgd2F5IHRvbyB2YWd1ZSk/Cj4gV2hhdAo+IGlzIHJlYWQtb25seSBzdXBwb3NlZCB0
byBtZWFuIGhlcmU/Cj4KPiBIYWlqdW46IEluIGZhY3QgYWxtb3N0IGFsbCBib2FyZCBoYXMgaXRz
IHNwZWNpYWwgQ1BMRC4gVGhpcyBub2RlIGp1c3QKPiBjb3B5IGZyb20gcDEwMjByZGItcGMgYm9h
cmQuCj4KPiBTbywgY2hhbmdlIGl0IHRvIDoKPgo+IGNwbGRAMiwwIHsKPiAgICAgICAgICAgY29t
cGF0aWJsZSA9ICJmc2wsIHAxMDIwcmRiLWNwbGQiOwo+ICAgICAgICAgICByZWcgPSA8MHgyIDB4
MCAweDIwMDAwPjsKPiAgICAgICAgICAgcmVhZC1vbmx5Owo+IH07CgpBZ2Fpbiwgd2hhdCBpcyBy
ZWFkLW9ubHkgc3VwcG9zZWQgdG8gbWVhbiBoZXJlPyAgSSBkb24ndCBjYXJlIHRoYXQgaXQncwpj
b3BpZWQgZnJvbSB0aGUgUEMgdmVyc2lvbi4gIEl0IGRvZXNuJ3QgbWFrZSBzZW5zZSwgYW5kIGlz
IG5vdApkb2N1bWVudGVkIGluIGEgYmluZGluZy4KCk1vc3RseSBDUExEIG9ubHkgdXNlZCB0byBy
ZWFkIGNvbmZpZ3VyYXRpb24gZnJvbS4gU3VwcG9zZWQgbm90IGJlZW4gY2hhbmdlZC4KCklzIHRo
ZSAtcGQgQ1BMRCAxMDAlIGlkZW50aWNhbCB0byB0aGUgLXBjIENQTEQ/ICBJZiBub3QsIHNob3Vs
ZG4ndCB0aGUKY29tcGF0aWJsZSBub3RlIHRoZSBkaWZmZXJlbmNlIGJldHdlZW4gdGhlIHR3bz8K
Cm9oLCB5ZXMgdGhleSBzaG91bGQgaGFkIHRoZWlyIG93biBuYW1lLiBJJ2xsIGNoYW5nZSBpdC4K
Ci1TY290dAo=

Re: 答复: 答复: [PATCH 2/2] powerpc/85xx: add the P1020RDB-PD DTS support

[Scott Wood]

On 07/09/2013 12:34:34 AM, Zhang Haijun-B42677 wrote:
> > cpld@2,0 {
> >           compatible =3D "fsl, p1020rdb-cpld";
> >           reg =3D <0x2 0x0 0x20000>;
> >           read-only;
> > };
>=20
> Again, what is read-only supposed to mean here?  I don't care that =20
> it's
> copied from the PC version.  It doesn't make sense, and is not
> documented in a binding.
>=20
> Mostly CPLD only used to read configuration from. Supposed not been =20
> changed.

The device tree describes the hardware, not the intended use (the =20
partition stuff is not a good example).  Plus, any property you use =20
must be documented in a binding.

And please use proper quoting in your e-mail replies.  Don't just =20
insert your response as if it were part of what I wrote.  You should be =20
able to make your e-mail client do this automatically (if you can't, =20
get a new e-mail client).

-Scott=