From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from ch1outboundpool.messaging.microsoft.com (ch1ehsobe005.messaging.microsoft.com [216.32.181.185]) (using TLSv1 with cipher AES128-SHA (128/128 bits)) (Client CN "mail.global.frontbridge.com", Issuer "MSIT Machine Auth CA 2" (not verified)) by ozlabs.org (Postfix) with ESMTPS id 403922C00CF for ; Tue, 30 Jul 2013 10:00:59 +1000 (EST) Date: Mon, 29 Jul 2013 19:00:51 -0500 From: Scott Wood Subject: Re: [PATCH] Add device file bindings for MAPLE To: Shaveta Leekha References: <1374930222-32739-1-git-send-email-shaveta@freescale.com> In-Reply-To: <1374930222-32739-1-git-send-email-shaveta@freescale.com> (from shaveta@freescale.com on Sat Jul 27 08:03:42 2013) Message-ID: <1375142451.30721.68@snotra> MIME-Version: 1.0 Content-Type: text/plain; charset="us-ascii"; delsp=Yes; format=Flowed Cc: Shaveta Leekha , devicetree-discuss@lists.ozlabs.org, linuxppc-dev@lists.ozlabs.org List-Id: Linux on PowerPC Developers Mail List List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , On 07/27/2013 08:03:42 AM, Shaveta Leekha wrote: > Signed-off-by: Shaveta Leekha > --- > .../devicetree/bindings/powerpc/fsl/maple.txt | 50 =20 > ++++++++++++++++++++ > 1 files changed, 50 insertions(+), 0 deletions(-) > create mode 100644 =20 > Documentation/devicetree/bindings/powerpc/fsl/maple.txt >=20 > diff --git a/Documentation/devicetree/bindings/powerpc/fsl/maple.txt =20 > b/Documentation/devicetree/bindings/powerpc/fsl/maple.txt > new file mode 100644 > index 0000000..23b80a7 > --- /dev/null > +++ b/Documentation/devicetree/bindings/powerpc/fsl/maple.txt > @@ -0,0 +1,50 @@ > +* Freescale MAPLE Multi Accelerator Platform Engine Baseband 3 > + (MAPLE-B3)device nodes > + > +Supported chips: > +Example: B4860 > + > +Required properties: > + > +- compatible: Should contain "fsl,maple-b3" as the value > + This identifies Multi Accelerator Platform Engine > + Baseband 3 block. > + > +- reg: offset and length of the register set for the =20 > device > + > +- interrupts > + Usage: required > + Value type: > + Definition: Specifies the interrupts generated by this =20 > device. The > + value of the interrupts property consists of =20 > one interrupt > + specifier. The format of the specifier is =20 > defined by the > + binding document describing the node's =20 > interrupt parent. Please clean up whitespace so the text aligns. > + > + A single IRQ that handles error conditions is specified =20 > by > + this property. (Typically shared with port-write). > + > +Devices that have LIODNs need to specify links to the parent PAMU =20 > controller > +(the actual PAMU controller that this device is connected to) and a =20 > pointer to > +the LIODN register, if applicable. > + > +- fsl,iommu-parent > + : > + This property should be present > + > +- status =3D "disabled" > + In this example, status is set "disabled", > + As Maple device wouldn't be used by PPC Linux. This =20 > representation is required > + for doing the PAMU programming on the Linux side. Is it proper for Linux to even set the LIODN on a device that is =20 "disabled"? Perhaps the compatible should be different, such as =20 "fsl,maple-b3-liodn" to indicate that that is the only portion of the =20 device that is owned by this partition. > +Example: > + /* B4860 */ > + > + maple@800000 { > + #address-cells =3D <0>; > + #size-cells =3D <0>; > + status =3D "disabled"; > + compatible =3D "fsl,maple-b3"; > + reg =3D <0x8000000 0x10000>; > + interrupts =3D <16 2 1 18>; > + fsl,iommu-parent =3D <&pamu1>; > + }; This error interrupt is documented as 13, not 18. b4860 (and maybe =20 other b4?) have an erratum that says that error interrupts are =20 reversed, but this is generally implemented in b4si-post.dtsi, not in =20 block-specific include files. Will no chip without the erratum ever =20 have maple? -Scott=