From: Minghuan Lian <Minghuan.Lian@freescale.com>
To: <linuxppc-dev@lists.ozlabs.org>
Cc: Scott Wood <scottwood@freescale.com>,
Minghuan Lian <Minghuan.Lian@freescale.com>,
Zang Roy-R61911 <r61911@freescale.com>
Subject: [PATCH] powerpc/dts: fix sRIO error interrupt for b4860
Date: Wed, 31 Jul 2013 10:59:07 +0800 [thread overview]
Message-ID: <1375239547-8259-1-git-send-email-Minghuan.Lian@freescale.com> (raw)
For B4 platform, MPIC EISR register is in reversed bitmap order,
instead of "Error interrupt source 0-31. Bit 0 represents SRC0."
the correct ordering is "Error interrupt source 0-31. Bit 0
represents SRC31." This patch is to fix sRIO EISR bit value
of error interrupt in dts node.
Signed-off-by: Minghuan Lian <Minghuan.Lian@freescale.com>
---
arch/powerpc/boot/dts/fsl/b4860si-post.dtsi | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/arch/powerpc/boot/dts/fsl/b4860si-post.dtsi b/arch/powerpc/boot/dts/fsl/b4860si-post.dtsi
index e5cf6c8..9813975 100644
--- a/arch/powerpc/boot/dts/fsl/b4860si-post.dtsi
+++ b/arch/powerpc/boot/dts/fsl/b4860si-post.dtsi
@@ -41,7 +41,7 @@
&rio {
compatible = "fsl,srio";
- interrupts = <16 2 1 11>;
+ interrupts = <16 2 1 20>;
#address-cells = <2>;
#size-cells = <2>;
fsl,iommu-parent = <&pamu0>;
--
1.8.1.2
reply other threads:[~2013-07-31 2:58 UTC|newest]
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