Re: [PATCH] powerpc: add the missing required isync for the coherent icache flush

[Benjamin Herrenschmidt <benh@kernel.crashing.org>]

On Tue, 2013-08-20 at 20:16 +0800, Kevin Hao wrote:

> Dummy question: What does the ifetch buffers mean? The instruction fetch
> pipeline or instruction dispatch pipeline? Shouldn't all the prefetched
> instructions in these buffers be discarded by isync?

Architecturally isync doesn't have to toss prefetch completely. It only
needs to make sense that context changes performed by previous
instructions (and interrupts/traps) happen at the point of the isync,
for example, it will ensure that a trap conditional is fully evaluated
before subsequent instruction execution, etc....

So in this case, it makes sure the icbi has been executed and it's the
icbi that invalidates the prefetched instructions.

> 
> >, sync orders the icbi and isync ensures its execution has been
> > synchronized. At least I *think* that's the required sequence, I have to
> > dbl check the arch, maybe tomorrow. I wouldn't be surprise if we also
> > need a sync before the icbi to order the actual stores to memory that
> > might have modified instructions with the icbi.
> 
> Doesn't the coherence between icache and dcache be maintained by the snooping?

The icache yes, but not the ifetch buffers (basically think of them as
buffering stages between icache and dispatch). At least that's my
understanding of the implementation. 

Cheers,
Ben.

> Thanks,
> Kevin
> 
> > 
> > Cheers,
> > Ben.
> > 
> > > diff --git a/arch/powerpc/kernel/misc_64.S b/arch/powerpc/kernel/misc_64.S
> > > index d74fefb..8fcdec7 100644
> > > --- a/arch/powerpc/kernel/misc_64.S
> > > +++ b/arch/powerpc/kernel/misc_64.S
> > > @@ -69,6 +69,8 @@ PPC64_CACHES:
> > >  
> > >  _KPROBE(flush_icache_range)
> > >  BEGIN_FTR_SECTION
> > > +	icbi	0,r3
> > > +	sync
> > >  	isync
> > >  	blr
> > >  END_FTR_SECTION_IFSET(CPU_FTR_COHERENT_ICACHE)
> > > @@ -209,6 +211,8 @@ _GLOBAL(flush_inval_dcache_range)
> > >   */
> > >  _GLOBAL(__flush_dcache_icache)
> > >  BEGIN_FTR_SECTION
> > > +	icbi	0,r3
> > > +	sync
> > >  	isync
> > >  	blr
> > >  END_FTR_SECTION_IFSET(CPU_FTR_COHERENT_ICACHE)
> > > 
> > > Thanks,
> > > Kevin
> > > 
> > > > 
> > > > Cheers,
> > > > Ben.
> > > > 
> > > > > Cheers,
> > > > > Ben.
> > > > > 
> > > > > > >  	blr
> > > > > > >  END_FTR_SECTION_IFSET(CPU_FTR_COHERENT_ICACHE)
> > > > > > >  	rlwinm	r3,r3,0,0,31-PAGE_SHIFT		/* Get page base address
> > > > > > > */
> > > > > > > @@ -474,6 +475,7 @@ END_MMU_FTR_SECTION_IFSET(MMU_FTR_TYPE_44x)
> > > > > > >   */
> > > > > > >  _GLOBAL(__flush_dcache_icache_phys)
> > > > > > >  BEGIN_FTR_SECTION
> > > > > > > +	isync
> > > > > > >  	blr					/* for 601, do nothing */
> > > > > > >  END_FTR_SECTION_IFSET(CPU_FTR_COHERENT_ICACHE)
> > > > > > >  	mfmsr	r10
> > > > > > > diff --git a/arch/powerpc/kernel/misc_64.S
> > > > > > > b/arch/powerpc/kernel/misc_64.S
> > > > > > > index 992a78e..d74fefb 100644
> > > > > > > --- a/arch/powerpc/kernel/misc_64.S
> > > > > > > +++ b/arch/powerpc/kernel/misc_64.S
> > > > > > > @@ -69,6 +69,7 @@ PPC64_CACHES:
> > > > > > > 
> > > > > > >  _KPROBE(flush_icache_range)
> > > > > > >  BEGIN_FTR_SECTION
> > > > > > > +	isync
> > > > > > >  	blr
> > > > > > >  END_FTR_SECTION_IFSET(CPU_FTR_COHERENT_ICACHE)
> > > > > > >  /*
> > > > > > > --
> > > > > > > 1.8.3.1
> > > > > > > 
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> > > > > > 
> > > > > 
> > > > 
> > > > 
> > 
> >