* [PATCH v2 1/3] powerpc/fsl: add E6500 PVR and SPRN_PWRMGTCR0 define @ 2013-08-27 8:41 Dongsheng Wang 2013-08-27 8:41 ` [PATCH v2 2/3] powerpc/85xx: add hardware automatically enter altivec idle state Dongsheng Wang 2013-08-27 8:41 ` [PATCH v2 3/3] powerpc/85xx: add hardware automatically enter pw20 state Dongsheng Wang 0 siblings, 2 replies; 5+ messages in thread From: Dongsheng Wang @ 2013-08-27 8:41 UTC (permalink / raw) To: scottwood, galak; +Cc: linuxppc-dev, Wang Dongsheng From: Wang Dongsheng <dongsheng.wang@freescale.com> E6500 PVR and SPRN_PWRMGTCR0 will be used in subsequent pw20/altivec idle patches. Signed-off-by: Wang Dongsheng <dongsheng.wang@freescale.com> diff --git a/arch/powerpc/include/asm/reg.h b/arch/powerpc/include/asm/reg.h index 64264bf..d4160ca 100644 --- a/arch/powerpc/include/asm/reg.h +++ b/arch/powerpc/include/asm/reg.h @@ -1053,6 +1053,8 @@ #define PVR_8560 0x80200000 #define PVR_VER_E500V1 0x8020 #define PVR_VER_E500V2 0x8021 +#define PVR_VER_E6500 0x8040 + /* * For the 8xx processors, all of them report the same PVR family for * the PowerPC core. The various versions of these processors must be diff --git a/arch/powerpc/include/asm/reg_booke.h b/arch/powerpc/include/asm/reg_booke.h index ed8f836..86ede76 100644 --- a/arch/powerpc/include/asm/reg_booke.h +++ b/arch/powerpc/include/asm/reg_booke.h @@ -170,6 +170,7 @@ #define SPRN_L2CSR1 0x3FA /* L2 Data Cache Control and Status Register 1 */ #define SPRN_DCCR 0x3FA /* Data Cache Cacheability Register */ #define SPRN_ICCR 0x3FB /* Instruction Cache Cacheability Register */ +#define SPRN_PWRMGTCR0 0x3FB /* Power management control register 0 */ #define SPRN_SVR 0x3FF /* System Version Register */ /* -- 1.8.0 ^ permalink raw reply related [flat|nested] 5+ messages in thread
* [PATCH v2 2/3] powerpc/85xx: add hardware automatically enter altivec idle state 2013-08-27 8:41 [PATCH v2 1/3] powerpc/fsl: add E6500 PVR and SPRN_PWRMGTCR0 define Dongsheng Wang @ 2013-08-27 8:41 ` Dongsheng Wang 2013-08-28 6:08 ` Wang Dongsheng-B40534 2013-08-27 8:41 ` [PATCH v2 3/3] powerpc/85xx: add hardware automatically enter pw20 state Dongsheng Wang 1 sibling, 1 reply; 5+ messages in thread From: Dongsheng Wang @ 2013-08-27 8:41 UTC (permalink / raw) To: scottwood, galak; +Cc: linuxppc-dev, Wang Dongsheng From: Wang Dongsheng <dongsheng.wang@freescale.com> Each core's AltiVec unit may be placed into a power savings mode by turning off power to the unit. Core hardware will automatically power down the AltiVec unit after no AltiVec instructions have executed in N cycles. The AltiVec power-control is triggered by hardware. Signed-off-by: Wang Dongsheng <dongsheng.wang@freescale.com> --- *v2: Remove: delete setup_idle_hw_governor function. delete "Fix erratum" for rev1. Move: move setup_* into __setup/restore_cpu_e6500. diff --git a/arch/powerpc/include/asm/reg_booke.h b/arch/powerpc/include/asm/reg_booke.h index 86ede76..8364bbe 100644 --- a/arch/powerpc/include/asm/reg_booke.h +++ b/arch/powerpc/include/asm/reg_booke.h @@ -217,6 +217,9 @@ #define CCR1_DPC 0x00000100 /* Disable L1 I-Cache/D-Cache parity checking */ #define CCR1_TCS 0x00000080 /* Timer Clock Select */ +/* Bit definitions for PWRMGTCR0. */ +#define PWRMGTCR0_ALTIVEC_IDLE (1 << 22) /* Altivec idle enable */ + /* Bit definitions for the MCSR. */ #define MCSR_MCS 0x80000000 /* Machine Check Summary */ #define MCSR_IB 0x40000000 /* Instruction PLB Error */ diff --git a/arch/powerpc/kernel/cpu_setup_fsl_booke.S b/arch/powerpc/kernel/cpu_setup_fsl_booke.S index bfb18c7..90bbb46 100644 --- a/arch/powerpc/kernel/cpu_setup_fsl_booke.S +++ b/arch/powerpc/kernel/cpu_setup_fsl_booke.S @@ -58,6 +58,7 @@ _GLOBAL(__setup_cpu_e6500) #ifdef CONFIG_PPC64 bl .setup_altivec_ivors #endif + bl setup_altivec_idle bl __setup_cpu_e5500 mtlr r6 blr @@ -119,6 +120,7 @@ _GLOBAL(__setup_cpu_e5500) _GLOBAL(__restore_cpu_e6500) mflr r5 bl .setup_altivec_ivors + bl setup_altivec_idle bl __restore_cpu_e5500 mtlr r5 blr diff --git a/arch/powerpc/platforms/85xx/common.c b/arch/powerpc/platforms/85xx/common.c index d0861a0..93b563b 100644 --- a/arch/powerpc/platforms/85xx/common.c +++ b/arch/powerpc/platforms/85xx/common.c @@ -11,6 +11,16 @@ #include "mpc85xx.h" +#define MAX_BIT 64 + +#define ALTIVEC_COUNT_OFFSET 16 +#define ALTIVEC_IDLE_COUNT_MASK 0x003f0000 + +/* + * FIXME - We don't know the AltiVec application scenarios. + */ +#define ALTIVEC_IDLE_TIME_BIT 14 /* 1ms */ + static struct of_device_id __initdata mpc85xx_common_ids[] = { { .type = "soc", }, { .compatible = "soc", }, @@ -80,3 +90,38 @@ void __init mpc85xx_cpm2_pic_init(void) irq_set_chained_handler(irq, cpm2_cascade); } #endif + +static bool has_pw20_altivec_idle(void) +{ + u32 pvr; + + pvr = mfspr(SPRN_PVR); + + /* PW20 & AltiVec idle feature only exists for E6500 */ + if (PVR_VER(pvr) != PVR_VER_E6500) + return false; + + return true; +} + +void setup_altivec_idle(void) +{ + u32 altivec_idle; + + if (!has_pw20_altivec_idle()) + return; + + /* Enable Altivec Idle */ + altivec_idle = mfspr(SPRN_PWRMGTCR0); + altivec_idle |= PWRMGTCR0_ALTIVEC_IDLE; + + /* Set Automatic AltiVec Idle Count */ + /* clear count */ + altivec_idle &= ~ALTIVEC_IDLE_COUNT_MASK; + + /* set count */ + altivec_idle |= + ((MAX_BIT - ALTIVEC_IDLE_TIME_BIT) << ALTIVEC_COUNT_OFFSET); + + mtspr(SPRN_PWRMGTCR0, altivec_idle); +} -- 1.8.0 ^ permalink raw reply related [flat|nested] 5+ messages in thread
* RE: [PATCH v2 2/3] powerpc/85xx: add hardware automatically enter altivec idle state 2013-08-27 8:41 ` [PATCH v2 2/3] powerpc/85xx: add hardware automatically enter altivec idle state Dongsheng Wang @ 2013-08-28 6:08 ` Wang Dongsheng-B40534 0 siblings, 0 replies; 5+ messages in thread From: Wang Dongsheng-B40534 @ 2013-08-28 6:08 UTC (permalink / raw) To: Wang Dongsheng-B40534, Wood Scott-B07421, galak@kernel.crashing.org Cc: linuxppc-dev@lists.ozlabs.org > -----Original Message----- > From: Wang Dongsheng-B40534 > Sent: Tuesday, August 27, 2013 4:42 PM > To: Wood Scott-B07421; galak@kernel.crashing.org > Cc: linuxppc-dev@lists.ozlabs.org; Wang Dongsheng-B40534 > Subject: [PATCH v2 2/3] powerpc/85xx: add hardware automatically enter > altivec idle state >=20 > From: Wang Dongsheng <dongsheng.wang@freescale.com> >=20 > Each core's AltiVec unit may be placed into a power savings mode > by turning off power to the unit. Core hardware will automatically > power down the AltiVec unit after no AltiVec instructions have > executed in N cycles. The AltiVec power-control is triggered by hardware. >=20 > Signed-off-by: Wang Dongsheng <dongsheng.wang@freescale.com> > --- > *v2: > Remove: > delete setup_idle_hw_governor function. > delete "Fix erratum" for rev1. >=20 > Move: > move setup_* into __setup/restore_cpu_e6500. >=20 > diff --git a/arch/powerpc/include/asm/reg_booke.h > b/arch/powerpc/include/asm/reg_booke.h > index 86ede76..8364bbe 100644 > --- a/arch/powerpc/include/asm/reg_booke.h > +++ b/arch/powerpc/include/asm/reg_booke.h > @@ -217,6 +217,9 @@ > #define CCR1_DPC 0x00000100 /* Disable L1 I-Cache/D-Cache parity > checking */ > #define CCR1_TCS 0x00000080 /* Timer Clock Select */ >=20 > +/* Bit definitions for PWRMGTCR0. */ > +#define PWRMGTCR0_ALTIVEC_IDLE (1 << 22) /* Altivec idle enable */ > + > /* Bit definitions for the MCSR. */ > #define MCSR_MCS 0x80000000 /* Machine Check Summary */ > #define MCSR_IB 0x40000000 /* Instruction PLB Error */ > diff --git a/arch/powerpc/kernel/cpu_setup_fsl_booke.S > b/arch/powerpc/kernel/cpu_setup_fsl_booke.S > index bfb18c7..90bbb46 100644 > --- a/arch/powerpc/kernel/cpu_setup_fsl_booke.S > +++ b/arch/powerpc/kernel/cpu_setup_fsl_booke.S > @@ -58,6 +58,7 @@ _GLOBAL(__setup_cpu_e6500) > #ifdef CONFIG_PPC64 > bl .setup_altivec_ivors > #endif > + bl setup_altivec_idle > bl __setup_cpu_e5500 > mtlr r6 > blr > @@ -119,6 +120,7 @@ _GLOBAL(__setup_cpu_e5500) > _GLOBAL(__restore_cpu_e6500) > mflr r5 > bl .setup_altivec_ivors > + bl setup_altivec_idle > bl __restore_cpu_e5500 > mtlr r5 > blr > diff --git a/arch/powerpc/platforms/85xx/common.c > b/arch/powerpc/platforms/85xx/common.c > index d0861a0..93b563b 100644 > --- a/arch/powerpc/platforms/85xx/common.c > +++ b/arch/powerpc/platforms/85xx/common.c > @@ -11,6 +11,16 @@ >=20 > #include "mpc85xx.h" >=20 > +#define MAX_BIT 64 > + This should be change to 63, i will fix this in next patch. - dongsheng ^ permalink raw reply [flat|nested] 5+ messages in thread
* [PATCH v2 3/3] powerpc/85xx: add hardware automatically enter pw20 state 2013-08-27 8:41 [PATCH v2 1/3] powerpc/fsl: add E6500 PVR and SPRN_PWRMGTCR0 define Dongsheng Wang 2013-08-27 8:41 ` [PATCH v2 2/3] powerpc/85xx: add hardware automatically enter altivec idle state Dongsheng Wang @ 2013-08-27 8:41 ` Dongsheng Wang 2013-09-05 18:56 ` Scott Wood 1 sibling, 1 reply; 5+ messages in thread From: Dongsheng Wang @ 2013-08-27 8:41 UTC (permalink / raw) To: scottwood, galak; +Cc: linuxppc-dev, Wang Dongsheng From: Wang Dongsheng <dongsheng.wang@freescale.com> Using hardware features make core automatically enter PW20 state. Set a TB count to hardware, the effective count begins when PW10 is entered. When the effective period has expired, the core will proceed from PW10 to PW20 if no exit conditions have occurred during the period. Signed-off-by: Wang Dongsheng <dongsheng.wang@freescale.com> --- Remove: delete setup_idle_hw_governor function. delete "Fix erratum" for rev1. Move: move setup_* into __setup/restore_cpu_e6500. diff --git a/arch/powerpc/include/asm/reg_booke.h b/arch/powerpc/include/asm/reg_booke.h index 8364bbe..e846495 100644 --- a/arch/powerpc/include/asm/reg_booke.h +++ b/arch/powerpc/include/asm/reg_booke.h @@ -219,6 +219,7 @@ /* Bit definitions for PWRMGTCR0. */ #define PWRMGTCR0_ALTIVEC_IDLE (1 << 22) /* Altivec idle enable */ +#define PWRMGTCR0_PW20_WAIT (1 << 14) /* PW20 state enable bit */ /* Bit definitions for the MCSR. */ #define MCSR_MCS 0x80000000 /* Machine Check Summary */ diff --git a/arch/powerpc/kernel/cpu_setup_fsl_booke.S b/arch/powerpc/kernel/cpu_setup_fsl_booke.S index 90bbb46..295ccb5 100644 --- a/arch/powerpc/kernel/cpu_setup_fsl_booke.S +++ b/arch/powerpc/kernel/cpu_setup_fsl_booke.S @@ -59,6 +59,7 @@ _GLOBAL(__setup_cpu_e6500) bl .setup_altivec_ivors #endif bl setup_altivec_idle + bl setup_pw20_idle bl __setup_cpu_e5500 mtlr r6 blr @@ -121,6 +122,7 @@ _GLOBAL(__restore_cpu_e6500) mflr r5 bl .setup_altivec_ivors bl setup_altivec_idle + bl setup_pw20_idle bl __restore_cpu_e5500 mtlr r5 blr diff --git a/arch/powerpc/platforms/85xx/common.c b/arch/powerpc/platforms/85xx/common.c index 93b563b..cdd526e 100644 --- a/arch/powerpc/platforms/85xx/common.c +++ b/arch/powerpc/platforms/85xx/common.c @@ -15,12 +15,22 @@ #define ALTIVEC_COUNT_OFFSET 16 #define ALTIVEC_IDLE_COUNT_MASK 0x003f0000 +#define PW20_COUNT_OFFSET 8 +#define PW20_IDLE_COUNT_MASK 0x00003f00 /* * FIXME - We don't know the AltiVec application scenarios. */ #define ALTIVEC_IDLE_TIME_BIT 14 /* 1ms */ +/* + * FIXME - We don't know, what time should we let the core into PW20 state. + * because we don't know the current state of the cpu load. And threads are + * independent, so we can not know the state of different thread has been + * idle. + */ +#define PW20_IDLE_TIME_BIT 14 /* 1ms */ + static struct of_device_id __initdata mpc85xx_common_ids[] = { { .type = "soc", }, { .compatible = "soc", }, @@ -125,3 +135,25 @@ void setup_altivec_idle(void) mtspr(SPRN_PWRMGTCR0, altivec_idle); } + +void setup_pw20_idle(void) +{ + u32 pw20_idle; + + if (!has_pw20_altivec_idle()) + return; + + pw20_idle = mfspr(SPRN_PWRMGTCR0); + + /* Set PW20_WAIT bit, Enable PW20 State */ + pw20_idle |= PWRMGTCR0_PW20_WAIT; + + /* Set Automatic PW20 Core Idle Count */ + /* clear count */ + pw20_idle &= ~PW20_IDLE_COUNT_MASK; + + /* set count */ + pw20_idle |= ((MAX_BIT - PW20_IDLE_TIME_BIT) << PW20_COUNT_OFFSET); + + mtspr(SPRN_PWRMGTCR0, pw20_idle); +} -- 1.8.0 ^ permalink raw reply related [flat|nested] 5+ messages in thread
* Re: [PATCH v2 3/3] powerpc/85xx: add hardware automatically enter pw20 state 2013-08-27 8:41 ` [PATCH v2 3/3] powerpc/85xx: add hardware automatically enter pw20 state Dongsheng Wang @ 2013-09-05 18:56 ` Scott Wood 0 siblings, 0 replies; 5+ messages in thread From: Scott Wood @ 2013-09-05 18:56 UTC (permalink / raw) To: Dongsheng Wang; +Cc: linuxppc-dev On Tue, 2013-08-27 at 16:41 +0800, Dongsheng Wang wrote: > From: Wang Dongsheng <dongsheng.wang@freescale.com> > > Using hardware features make core automatically enter PW20 state. > Set a TB count to hardware, the effective count begins when PW10 > is entered. When the effective period has expired, the core will > proceed from PW10 to PW20 if no exit conditions have occurred during > the period. > > Signed-off-by: Wang Dongsheng <dongsheng.wang@freescale.com> > --- > Remove: > delete setup_idle_hw_governor function. > delete "Fix erratum" for rev1. > > Move: > move setup_* into __setup/restore_cpu_e6500. > > diff --git a/arch/powerpc/include/asm/reg_booke.h b/arch/powerpc/include/asm/reg_booke.h > index 8364bbe..e846495 100644 > --- a/arch/powerpc/include/asm/reg_booke.h > +++ b/arch/powerpc/include/asm/reg_booke.h > @@ -219,6 +219,7 @@ > > /* Bit definitions for PWRMGTCR0. */ > #define PWRMGTCR0_ALTIVEC_IDLE (1 << 22) /* Altivec idle enable */ > +#define PWRMGTCR0_PW20_WAIT (1 << 14) /* PW20 state enable bit */ > > /* Bit definitions for the MCSR. */ > #define MCSR_MCS 0x80000000 /* Machine Check Summary */ > diff --git a/arch/powerpc/kernel/cpu_setup_fsl_booke.S b/arch/powerpc/kernel/cpu_setup_fsl_booke.S > index 90bbb46..295ccb5 100644 > --- a/arch/powerpc/kernel/cpu_setup_fsl_booke.S > +++ b/arch/powerpc/kernel/cpu_setup_fsl_booke.S > @@ -59,6 +59,7 @@ _GLOBAL(__setup_cpu_e6500) > bl .setup_altivec_ivors > #endif > bl setup_altivec_idle > + bl setup_pw20_idle > bl __setup_cpu_e5500 > mtlr r6 > blr > @@ -121,6 +122,7 @@ _GLOBAL(__restore_cpu_e6500) > mflr r5 > bl .setup_altivec_ivors > bl setup_altivec_idle > + bl setup_pw20_idle > bl __restore_cpu_e5500 > mtlr r5 > blr > diff --git a/arch/powerpc/platforms/85xx/common.c b/arch/powerpc/platforms/85xx/common.c > index 93b563b..cdd526e 100644 > --- a/arch/powerpc/platforms/85xx/common.c > +++ b/arch/powerpc/platforms/85xx/common.c > @@ -15,12 +15,22 @@ > > #define ALTIVEC_COUNT_OFFSET 16 > #define ALTIVEC_IDLE_COUNT_MASK 0x003f0000 > +#define PW20_COUNT_OFFSET 8 > +#define PW20_IDLE_COUNT_MASK 0x00003f00 > > /* > * FIXME - We don't know the AltiVec application scenarios. > */ > #define ALTIVEC_IDLE_TIME_BIT 14 /* 1ms */ > > +/* > + * FIXME - We don't know, what time should we let the core into PW20 state. > + * because we don't know the current state of the cpu load. And threads are > + * independent, so we can not know the state of different thread has been > + * idle. > + */ > +#define PW20_IDLE_TIME_BIT 14 /* 1ms */ > + > static struct of_device_id __initdata mpc85xx_common_ids[] = { > { .type = "soc", }, > { .compatible = "soc", }, > @@ -125,3 +135,25 @@ void setup_altivec_idle(void) > > mtspr(SPRN_PWRMGTCR0, altivec_idle); > } > + > +void setup_pw20_idle(void) > +{ > + u32 pw20_idle; > + > + if (!has_pw20_altivec_idle()) > + return; > + > + pw20_idle = mfspr(SPRN_PWRMGTCR0); > + > + /* Set PW20_WAIT bit, Enable PW20 State */ > + pw20_idle |= PWRMGTCR0_PW20_WAIT; > + > + /* Set Automatic PW20 Core Idle Count */ > + /* clear count */ > + pw20_idle &= ~PW20_IDLE_COUNT_MASK; > + > + /* set count */ > + pw20_idle |= ((MAX_BIT - PW20_IDLE_TIME_BIT) << PW20_COUNT_OFFSET); > + > + mtspr(SPRN_PWRMGTCR0, pw20_idle); > +} You can't call C code from __restore_cpu_e6500 as you don't have a stack yet. -Scott ^ permalink raw reply [flat|nested] 5+ messages in thread
end of thread, other threads:[~2013-09-05 18:57 UTC | newest] Thread overview: 5+ messages (download: mbox.gz follow: Atom feed -- links below jump to the message on this page -- 2013-08-27 8:41 [PATCH v2 1/3] powerpc/fsl: add E6500 PVR and SPRN_PWRMGTCR0 define Dongsheng Wang 2013-08-27 8:41 ` [PATCH v2 2/3] powerpc/85xx: add hardware automatically enter altivec idle state Dongsheng Wang 2013-08-28 6:08 ` Wang Dongsheng-B40534 2013-08-27 8:41 ` [PATCH v2 3/3] powerpc/85xx: add hardware automatically enter pw20 state Dongsheng Wang 2013-09-05 18:56 ` Scott Wood
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