* [PATCH v4 1/4] powerpc/fsl: add E6500 PVR and SPRN_PWRMGTCR0 define @ 2013-09-24 9:27 Dongsheng Wang 2013-09-24 11:21 ` Bhushan Bharat-R65777 0 siblings, 1 reply; 6+ messages in thread From: Dongsheng Wang @ 2013-09-24 9:27 UTC (permalink / raw) To: scottwood; +Cc: linuxppc-dev, Wang Dongsheng From: Wang Dongsheng <dongsheng.wang@freescale.com> E6500 PVR and SPRN_PWRMGTCR0 will be used in subsequent pw20/altivec idle patches. Signed-off-by: Wang Dongsheng <dongsheng.wang@freescale.com> --- *v3: Add bit definitions for PWRMGTCR0. arch/powerpc/include/asm/reg.h | 2 ++ arch/powerpc/include/asm/reg_booke.h | 9 +++++++++ 2 files changed, 11 insertions(+) diff --git a/arch/powerpc/include/asm/reg.h b/arch/powerpc/include/asm/reg.h index 64264bf..d4160ca 100644 --- a/arch/powerpc/include/asm/reg.h +++ b/arch/powerpc/include/asm/reg.h @@ -1053,6 +1053,8 @@ #define PVR_8560 0x80200000 #define PVR_VER_E500V1 0x8020 #define PVR_VER_E500V2 0x8021 +#define PVR_VER_E6500 0x8040 + /* * For the 8xx processors, all of them report the same PVR family for * the PowerPC core. The various versions of these processors must be diff --git a/arch/powerpc/include/asm/reg_booke.h b/arch/powerpc/include/asm/reg_booke.h index ed8f836..4a6457e 100644 --- a/arch/powerpc/include/asm/reg_booke.h +++ b/arch/powerpc/include/asm/reg_booke.h @@ -170,6 +170,7 @@ #define SPRN_L2CSR1 0x3FA /* L2 Data Cache Control and Status Register 1 */ #define SPRN_DCCR 0x3FA /* Data Cache Cacheability Register */ #define SPRN_ICCR 0x3FB /* Instruction Cache Cacheability Register */ +#define SPRN_PWRMGTCR0 0x3FB /* Power management control register 0 */ #define SPRN_SVR 0x3FF /* System Version Register */ /* @@ -216,6 +217,14 @@ #define CCR1_DPC 0x00000100 /* Disable L1 I-Cache/D-Cache parity checking */ #define CCR1_TCS 0x00000080 /* Timer Clock Select */ +/* Bit definitions for PWRMGTCR0. */ +#define PWRMGTCR0_PW20_WAIT (1 << 14) /* PW20 state enable bit */ +#define PWRMGTCR0_PW20_ENT_SHIFT 8 +#define PWRMGTCR0_PW20_ENT 0x3F00 +#define PWRMGTCR0_AV_IDLE_PD_EN (1 << 22) /* Altivec idle enable */ +#define PWRMGTCR0_AV_IDLE_CNT_SHIFT 16 +#define PWRMGTCR0_AV_IDLE_CNT 0x3F0000 + /* Bit definitions for the MCSR. */ #define MCSR_MCS 0x80000000 /* Machine Check Summary */ #define MCSR_IB 0x40000000 /* Instruction PLB Error */ -- 1.8.0 ^ permalink raw reply related [flat|nested] 6+ messages in thread
* RE: [PATCH v4 1/4] powerpc/fsl: add E6500 PVR and SPRN_PWRMGTCR0 define 2013-09-24 9:27 [PATCH v4 1/4] powerpc/fsl: add E6500 PVR and SPRN_PWRMGTCR0 define Dongsheng Wang @ 2013-09-24 11:21 ` Bhushan Bharat-R65777 2013-09-24 15:48 ` Kumar Gala 0 siblings, 1 reply; 6+ messages in thread From: Bhushan Bharat-R65777 @ 2013-09-24 11:21 UTC (permalink / raw) To: Wang Dongsheng-B40534, Wood Scott-B07421 Cc: Wang Dongsheng-B40534, linuxppc-dev@lists.ozlabs.org > -----Original Message----- > From: Linuxppc-dev [mailto:linuxppc-dev- > bounces+bharat.bhushan=3Dfreescale.com@lists.ozlabs.org] On Behalf Of Don= gsheng > Wang > Sent: Tuesday, September 24, 2013 2:58 PM > To: Wood Scott-B07421 > Cc: linuxppc-dev@lists.ozlabs.org; Wang Dongsheng-B40534 > Subject: [PATCH v4 1/4] powerpc/fsl: add E6500 PVR and SPRN_PWRMGTCR0 def= ine >=20 > From: Wang Dongsheng <dongsheng.wang@freescale.com> >=20 > E6500 PVR and SPRN_PWRMGTCR0 will be used in subsequent pw20/altivec idle > patches. >=20 > Signed-off-by: Wang Dongsheng <dongsheng.wang@freescale.com> > --- > *v3: > Add bit definitions for PWRMGTCR0. >=20 > arch/powerpc/include/asm/reg.h | 2 ++ > arch/powerpc/include/asm/reg_booke.h | 9 +++++++++ > 2 files changed, 11 insertions(+) >=20 > diff --git a/arch/powerpc/include/asm/reg.h b/arch/powerpc/include/asm/re= g.h > index 64264bf..d4160ca 100644 > --- a/arch/powerpc/include/asm/reg.h > +++ b/arch/powerpc/include/asm/reg.h > @@ -1053,6 +1053,8 @@ > #define PVR_8560 0x80200000 > #define PVR_VER_E500V1 0x8020 > #define PVR_VER_E500V2 0x8021 > +#define PVR_VER_E6500 0x8040 > + > /* > * For the 8xx processors, all of them report the same PVR family for > * the PowerPC core. The various versions of these processors must be di= ff -- > git a/arch/powerpc/include/asm/reg_booke.h > b/arch/powerpc/include/asm/reg_booke.h > index ed8f836..4a6457e 100644 > --- a/arch/powerpc/include/asm/reg_booke.h > +++ b/arch/powerpc/include/asm/reg_booke.h > @@ -170,6 +170,7 @@ > #define SPRN_L2CSR1 0x3FA /* L2 Data Cache Control and Status Register 1 > */ > #define SPRN_DCCR 0x3FA /* Data Cache Cacheability Register */ > #define SPRN_ICCR 0x3FB /* Instruction Cache Cacheability Register */ > +#define SPRN_PWRMGTCR0 0x3FB /* Power management control register 0 */ Is this generic for booke or e6500 specific? I can't see this register eith= er in ISA and EREF. Also I can see SPRN_ICCR also with same SPRN, how that is possible? -Bharat > #define SPRN_SVR 0x3FF /* System Version Register */ >=20 > /* > @@ -216,6 +217,14 @@ > #define CCR1_DPC 0x00000100 /* Disable L1 I-Cache/D-Cache parity > checking */ > #define CCR1_TCS 0x00000080 /* Timer Clock Select */ >=20 > +/* Bit definitions for PWRMGTCR0. */ > +#define PWRMGTCR0_PW20_WAIT (1 << 14) /* PW20 state enable bit */ > +#define PWRMGTCR0_PW20_ENT_SHIFT 8 > +#define PWRMGTCR0_PW20_ENT 0x3F00 > +#define PWRMGTCR0_AV_IDLE_PD_EN (1 << 22) /* Altivec idle enable */ > +#define PWRMGTCR0_AV_IDLE_CNT_SHIFT 16 > +#define PWRMGTCR0_AV_IDLE_CNT 0x3F0000 > + > /* Bit definitions for the MCSR. */ > #define MCSR_MCS 0x80000000 /* Machine Check Summary */ > #define MCSR_IB 0x40000000 /* Instruction PLB Error */ > -- > 1.8.0 >=20 >=20 > _______________________________________________ > Linuxppc-dev mailing list > Linuxppc-dev@lists.ozlabs.org > https://lists.ozlabs.org/listinfo/linuxppc-dev ^ permalink raw reply [flat|nested] 6+ messages in thread
* Re: [PATCH v4 1/4] powerpc/fsl: add E6500 PVR and SPRN_PWRMGTCR0 define 2013-09-24 11:21 ` Bhushan Bharat-R65777 @ 2013-09-24 15:48 ` Kumar Gala 2013-09-25 2:34 ` Wang Dongsheng-B40534 2013-09-25 3:42 ` Bhushan Bharat-R65777 0 siblings, 2 replies; 6+ messages in thread From: Kumar Gala @ 2013-09-24 15:48 UTC (permalink / raw) To: Bhushan Bharat-R65777 Cc: Wood Scott-B07421, Wang Dongsheng-B40534, linuxppc-dev@lists.ozlabs.org On Sep 24, 2013, at 6:21 AM, Bhushan Bharat-R65777 wrote: >=20 >=20 >> -----Original Message----- >> From: Linuxppc-dev [mailto:linuxppc-dev- >> bounces+bharat.bhushan=3Dfreescale.com@lists.ozlabs.org] On Behalf Of = Dongsheng >> Wang >> Sent: Tuesday, September 24, 2013 2:58 PM >> To: Wood Scott-B07421 >> Cc: linuxppc-dev@lists.ozlabs.org; Wang Dongsheng-B40534 >> Subject: [PATCH v4 1/4] powerpc/fsl: add E6500 PVR and SPRN_PWRMGTCR0 = define >>=20 >> From: Wang Dongsheng <dongsheng.wang@freescale.com> >>=20 >> E6500 PVR and SPRN_PWRMGTCR0 will be used in subsequent pw20/altivec = idle >> patches. >>=20 >> Signed-off-by: Wang Dongsheng <dongsheng.wang@freescale.com> >> --- >> *v3: >> Add bit definitions for PWRMGTCR0. >>=20 >> arch/powerpc/include/asm/reg.h | 2 ++ >> arch/powerpc/include/asm/reg_booke.h | 9 +++++++++ >> 2 files changed, 11 insertions(+) >>=20 >> diff --git a/arch/powerpc/include/asm/reg.h = b/arch/powerpc/include/asm/reg.h >> index 64264bf..d4160ca 100644 >> --- a/arch/powerpc/include/asm/reg.h >> +++ b/arch/powerpc/include/asm/reg.h >> @@ -1053,6 +1053,8 @@ >> #define PVR_8560 0x80200000 >> #define PVR_VER_E500V1 0x8020 >> #define PVR_VER_E500V2 0x8021 >> +#define PVR_VER_E6500 0x8040 >> + >> /* >> * For the 8xx processors, all of them report the same PVR family for >> * the PowerPC core. The various versions of these processors must be = diff -- >> git a/arch/powerpc/include/asm/reg_booke.h >> b/arch/powerpc/include/asm/reg_booke.h >> index ed8f836..4a6457e 100644 >> --- a/arch/powerpc/include/asm/reg_booke.h >> +++ b/arch/powerpc/include/asm/reg_booke.h >> @@ -170,6 +170,7 @@ >> #define SPRN_L2CSR1 0x3FA /* L2 Data Cache Control and Status = Register 1 >> */ >> #define SPRN_DCCR 0x3FA /* Data Cache Cacheability Register */ >> #define SPRN_ICCR 0x3FB /* Instruction Cache Cacheability = Register */ >> +#define SPRN_PWRMGTCR0 0x3FB /* Power management control = register 0 */ >=20 > Is this generic for booke or e6500 specific? I can't see this register = either in ISA and EREF. > Also I can see SPRN_ICCR also with same SPRN, how that is possible? Its possibly because the register maybe in implementation specific = region. I'm guessing ICCR is a 40x specific register. - k ^ permalink raw reply [flat|nested] 6+ messages in thread
* RE: [PATCH v4 1/4] powerpc/fsl: add E6500 PVR and SPRN_PWRMGTCR0 define 2013-09-24 15:48 ` Kumar Gala @ 2013-09-25 2:34 ` Wang Dongsheng-B40534 2013-09-25 3:42 ` Bhushan Bharat-R65777 1 sibling, 0 replies; 6+ messages in thread From: Wang Dongsheng-B40534 @ 2013-09-25 2:34 UTC (permalink / raw) To: Kumar Gala, Bhushan Bharat-R65777 Cc: Wood Scott-B07421, linuxppc-dev@lists.ozlabs.org > >> /* > >> * For the 8xx processors, all of them report the same PVR family for > >> * the PowerPC core. The various versions of these processors must be > >> diff -- git a/arch/powerpc/include/asm/reg_booke.h > >> b/arch/powerpc/include/asm/reg_booke.h > >> index ed8f836..4a6457e 100644 > >> --- a/arch/powerpc/include/asm/reg_booke.h > >> +++ b/arch/powerpc/include/asm/reg_booke.h > >> @@ -170,6 +170,7 @@ > >> #define SPRN_L2CSR1 0x3FA /* L2 Data Cache Control and Status > Register 1 > >> */ > >> #define SPRN_DCCR 0x3FA /* Data Cache Cacheability Register */ > >> #define SPRN_ICCR 0x3FB /* Instruction Cache Cacheability Register > */ > >> +#define SPRN_PWRMGTCR0 0x3FB /* Power management control register > 0 */ > > > > Is this generic for booke or e6500 specific? I can't see this register > either in ISA and EREF. Yes, now only e6500 have this register. There is no problem in this definit= ion, because no conflict in FSL platform. > > Also I can see SPRN_ICCR also with same SPRN, how that is possible? >=20 > Its possibly because the register maybe in implementation specific region= . > I'm guessing ICCR is a 40x specific register. Yes, kumar is right. Its use only in 4xx series of chips. ICTC(arch/powerpc/include/asm/reg.h) also use 0x3FB, Its use only in 6xx se= ries of chips. -dongsheng ^ permalink raw reply [flat|nested] 6+ messages in thread
* RE: [PATCH v4 1/4] powerpc/fsl: add E6500 PVR and SPRN_PWRMGTCR0 define 2013-09-24 15:48 ` Kumar Gala 2013-09-25 2:34 ` Wang Dongsheng-B40534 @ 2013-09-25 3:42 ` Bhushan Bharat-R65777 2013-09-25 5:08 ` Wang Dongsheng-B40534 1 sibling, 1 reply; 6+ messages in thread From: Bhushan Bharat-R65777 @ 2013-09-25 3:42 UTC (permalink / raw) To: Kumar Gala Cc: Wood Scott-B07421, Wang Dongsheng-B40534, linuxppc-dev@lists.ozlabs.org > -----Original Message----- > From: Kumar Gala [mailto:galak@kernel.crashing.org] > Sent: Tuesday, September 24, 2013 9:19 PM > To: Bhushan Bharat-R65777 > Cc: Wang Dongsheng-B40534; Wood Scott-B07421; linuxppc-dev@lists.ozlabs.o= rg > Subject: Re: [PATCH v4 1/4] powerpc/fsl: add E6500 PVR and SPRN_PWRMGTCR0= define >=20 >=20 > On Sep 24, 2013, at 6:21 AM, Bhushan Bharat-R65777 wrote: >=20 > > > > > >> -----Original Message----- > >> From: Linuxppc-dev [mailto:linuxppc-dev- > >> bounces+bharat.bhushan=3Dfreescale.com@lists.ozlabs.org] On Behalf Of > >> bounces+Dongsheng > >> Wang > >> Sent: Tuesday, September 24, 2013 2:58 PM > >> To: Wood Scott-B07421 > >> Cc: linuxppc-dev@lists.ozlabs.org; Wang Dongsheng-B40534 > >> Subject: [PATCH v4 1/4] powerpc/fsl: add E6500 PVR and SPRN_PWRMGTCR0 > >> define > >> > >> From: Wang Dongsheng <dongsheng.wang@freescale.com> > >> > >> E6500 PVR and SPRN_PWRMGTCR0 will be used in subsequent pw20/altivec > >> idle patches. > >> > >> Signed-off-by: Wang Dongsheng <dongsheng.wang@freescale.com> > >> --- > >> *v3: > >> Add bit definitions for PWRMGTCR0. > >> > >> arch/powerpc/include/asm/reg.h | 2 ++ > >> arch/powerpc/include/asm/reg_booke.h | 9 +++++++++ > >> 2 files changed, 11 insertions(+) > >> > >> diff --git a/arch/powerpc/include/asm/reg.h > >> b/arch/powerpc/include/asm/reg.h index 64264bf..d4160ca 100644 > >> --- a/arch/powerpc/include/asm/reg.h > >> +++ b/arch/powerpc/include/asm/reg.h > >> @@ -1053,6 +1053,8 @@ > >> #define PVR_8560 0x80200000 > >> #define PVR_VER_E500V1 0x8020 > >> #define PVR_VER_E500V2 0x8021 > >> +#define PVR_VER_E6500 0x8040 > >> + > >> /* > >> * For the 8xx processors, all of them report the same PVR family for > >> * the PowerPC core. The various versions of these processors must be > >> diff -- git a/arch/powerpc/include/asm/reg_booke.h > >> b/arch/powerpc/include/asm/reg_booke.h > >> index ed8f836..4a6457e 100644 > >> --- a/arch/powerpc/include/asm/reg_booke.h > >> +++ b/arch/powerpc/include/asm/reg_booke.h > >> @@ -170,6 +170,7 @@ > >> #define SPRN_L2CSR1 0x3FA /* L2 Data Cache Control and Status Register= 1 > >> */ > >> #define SPRN_DCCR 0x3FA /* Data Cache Cacheability Register */ > >> #define SPRN_ICCR 0x3FB /* Instruction Cache Cacheability Register */ > >> +#define SPRN_PWRMGTCR0 0x3FB /* Power management control register 0 *= / > > > > Is this generic for booke or e6500 specific? I can't see this register = either > in ISA and EREF. > > Also I can see SPRN_ICCR also with same SPRN, how that is possible? >=20 > Its possibly because the register maybe in implementation specific region= . I'm > guessing ICCR is a 40x specific register. Kumar, this seems to create confusion? Although I do not like so many heade= r files but still I think we can have reg_4xx.h, reg_fsl_booke.h etc for im= plementation specific definitions. -Bharat >=20 > - k >=20 ^ permalink raw reply [flat|nested] 6+ messages in thread
* RE: [PATCH v4 1/4] powerpc/fsl: add E6500 PVR and SPRN_PWRMGTCR0 define 2013-09-25 3:42 ` Bhushan Bharat-R65777 @ 2013-09-25 5:08 ` Wang Dongsheng-B40534 0 siblings, 0 replies; 6+ messages in thread From: Wang Dongsheng-B40534 @ 2013-09-25 5:08 UTC (permalink / raw) To: Bhushan Bharat-R65777, Kumar Gala Cc: Wood Scott-B07421, linuxppc-dev@lists.ozlabs.org > -----Original Message----- > From: Bhushan Bharat-R65777 > Sent: Wednesday, September 25, 2013 11:43 AM > To: Kumar Gala > Cc: Wang Dongsheng-B40534; Wood Scott-B07421; linuxppc- > dev@lists.ozlabs.org > Subject: RE: [PATCH v4 1/4] powerpc/fsl: add E6500 PVR and SPRN_PWRMGTCR0 > define >=20 >=20 >=20 > > -----Original Message----- > > From: Kumar Gala [mailto:galak@kernel.crashing.org] > > Sent: Tuesday, September 24, 2013 9:19 PM > > To: Bhushan Bharat-R65777 > > Cc: Wang Dongsheng-B40534; Wood Scott-B07421; > > linuxppc-dev@lists.ozlabs.org > > Subject: Re: [PATCH v4 1/4] powerpc/fsl: add E6500 PVR and > > SPRN_PWRMGTCR0 define > > > > > > On Sep 24, 2013, at 6:21 AM, Bhushan Bharat-R65777 wrote: > > > > > > > > > > >> -----Original Message----- > > >> From: Linuxppc-dev [mailto:linuxppc-dev- > > >> bounces+bharat.bhushan=3Dfreescale.com@lists.ozlabs.org] On Behalf O= f > > >> bounces+Dongsheng > > >> Wang > > >> Sent: Tuesday, September 24, 2013 2:58 PM > > >> To: Wood Scott-B07421 > > >> Cc: linuxppc-dev@lists.ozlabs.org; Wang Dongsheng-B40534 > > >> Subject: [PATCH v4 1/4] powerpc/fsl: add E6500 PVR and > > >> SPRN_PWRMGTCR0 define > > >> > > >> From: Wang Dongsheng <dongsheng.wang@freescale.com> > > >> > > >> E6500 PVR and SPRN_PWRMGTCR0 will be used in subsequent > > >> pw20/altivec idle patches. > > >> > > >> Signed-off-by: Wang Dongsheng <dongsheng.wang@freescale.com> > > >> --- > > >> *v3: > > >> Add bit definitions for PWRMGTCR0. > > >> > > >> arch/powerpc/include/asm/reg.h | 2 ++ > > >> arch/powerpc/include/asm/reg_booke.h | 9 +++++++++ > > >> 2 files changed, 11 insertions(+) > > >> > > >> diff --git a/arch/powerpc/include/asm/reg.h > > >> b/arch/powerpc/include/asm/reg.h index 64264bf..d4160ca 100644 > > >> --- a/arch/powerpc/include/asm/reg.h > > >> +++ b/arch/powerpc/include/asm/reg.h > > >> @@ -1053,6 +1053,8 @@ > > >> #define PVR_8560 0x80200000 > > >> #define PVR_VER_E500V1 0x8020 > > >> #define PVR_VER_E500V2 0x8021 > > >> +#define PVR_VER_E6500 0x8040 > > >> + > > >> /* > > >> * For the 8xx processors, all of them report the same PVR family > > >> for > > >> * the PowerPC core. The various versions of these processors must > > >> be diff -- git a/arch/powerpc/include/asm/reg_booke.h > > >> b/arch/powerpc/include/asm/reg_booke.h > > >> index ed8f836..4a6457e 100644 > > >> --- a/arch/powerpc/include/asm/reg_booke.h > > >> +++ b/arch/powerpc/include/asm/reg_booke.h > > >> @@ -170,6 +170,7 @@ > > >> #define SPRN_L2CSR1 0x3FA /* L2 Data Cache Control and Status > Register 1 > > >> */ > > >> #define SPRN_DCCR 0x3FA /* Data Cache Cacheability Register */ > > >> #define SPRN_ICCR 0x3FB /* Instruction Cache Cacheability Register > */ > > >> +#define SPRN_PWRMGTCR0 0x3FB /* Power management control register > 0 */ > > > > > > Is this generic for booke or e6500 specific? I can't see this > > > register either > > in ISA and EREF. > > > Also I can see SPRN_ICCR also with same SPRN, how that is possible? > > > > Its possibly because the register maybe in implementation specific > > region. I'm guessing ICCR is a 40x specific register. >=20 > Kumar, this seems to create confusion?=20 I don't think this define will create a confusion, because this is only SPR= number definition and we already have a document(like EREF, ISA, this register def= ine in E6500-EREF) to describe these registers. There are no conflicts and other p= latform and different platforms for the same register have different purposes, it l= ooks normal. Instead we should put together, so as to remind that the SPR will be reuse = from other platforms. -dongsheng ^ permalink raw reply [flat|nested] 6+ messages in thread
end of thread, other threads:[~2013-09-25 5:08 UTC | newest] Thread overview: 6+ messages (download: mbox.gz follow: Atom feed -- links below jump to the message on this page -- 2013-09-24 9:27 [PATCH v4 1/4] powerpc/fsl: add E6500 PVR and SPRN_PWRMGTCR0 define Dongsheng Wang 2013-09-24 11:21 ` Bhushan Bharat-R65777 2013-09-24 15:48 ` Kumar Gala 2013-09-25 2:34 ` Wang Dongsheng-B40534 2013-09-25 3:42 ` Bhushan Bharat-R65777 2013-09-25 5:08 ` Wang Dongsheng-B40534
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