* [PATCH V4 1/3] powerpc/85xx: Add QE common init functions @ 2013-09-24 10:48 Xie Xiaobo 2013-09-24 10:48 ` [PATCH V4 2/3] powerpc/85xx: Use common init functions for QE Xie Xiaobo ` (2 more replies) 0 siblings, 3 replies; 14+ messages in thread From: Xie Xiaobo @ 2013-09-24 10:48 UTC (permalink / raw) To: linuxppc-dev, scottwood; +Cc: Xie Xiaobo Define two QE init functions in common file, and avoid the same codes being duplicated in board files. Signed-off-by: Xie Xiaobo <X.Xie@freescale.com> --- V4 -> V3: Nochange arch/powerpc/platforms/85xx/common.c | 51 +++++++++++++++++++++++++++++++++++ arch/powerpc/platforms/85xx/mpc85xx.h | 8 ++++++ 2 files changed, 59 insertions(+) diff --git a/arch/powerpc/platforms/85xx/common.c b/arch/powerpc/platforms/85xx/common.c index d0861a0..08fff48 100644 --- a/arch/powerpc/platforms/85xx/common.c +++ b/arch/powerpc/platforms/85xx/common.c @@ -7,6 +7,9 @@ */ #include <linux/of_platform.h> +#include <asm/machdep.h> +#include <asm/qe.h> +#include <asm/qe_ic.h> #include <sysdev/cpm2_pic.h> #include "mpc85xx.h" @@ -80,3 +83,51 @@ void __init mpc85xx_cpm2_pic_init(void) irq_set_chained_handler(irq, cpm2_cascade); } #endif + +#ifdef CONFIG_QUICC_ENGINE +void __init mpc85xx_qe_pic_init(void) +{ + struct device_node *np; + + np = of_find_compatible_node(NULL, NULL, "fsl,qe-ic"); + if (np) { + if (machine_is(mpc8568_mds) || machine_is(mpc8569_mds)) + qe_ic_init(np, 0, qe_ic_cascade_muxed_mpic, NULL); + else + qe_ic_init(np, 0, qe_ic_cascade_low_mpic, + qe_ic_cascade_high_mpic); + of_node_put(np); + } else + pr_err("%s: Could not find qe-ic node\n", __func__); +} + +void __init mpc85xx_qe_init(void) +{ + struct device_node *np; + + np = of_find_compatible_node(NULL, NULL, "fsl,qe"); + if (!np) { + np = of_find_node_by_name(NULL, "qe"); + if (!np) { + pr_err("%s: Could not find Quicc Engine node\n", + __func__); + return; + } + } + + qe_reset(); + of_node_put(np); + + np = of_find_node_by_name(NULL, "par_io"); + if (np) { + struct device_node *ucc; + + par_io_init(np); + of_node_put(np); + + for_each_node_by_name(ucc, "ucc") + par_io_of_config(ucc); + + } +} +#endif diff --git a/arch/powerpc/platforms/85xx/mpc85xx.h b/arch/powerpc/platforms/85xx/mpc85xx.h index 2aa7c5d..1d39095 100644 --- a/arch/powerpc/platforms/85xx/mpc85xx.h +++ b/arch/powerpc/platforms/85xx/mpc85xx.h @@ -8,4 +8,12 @@ extern void mpc85xx_cpm2_pic_init(void); static inline void __init mpc85xx_cpm2_pic_init(void) {} #endif /* CONFIG_CPM2 */ +#ifdef CONFIG_QUICC_ENGINE +extern void mpc85xx_qe_pic_init(void); +extern void mpc85xx_qe_init(void); +#else +static inline void __init mpc85xx_qe_pic_init(void) {} +static inline void __init mpc85xx_qe_init(void) {} +#endif + #endif -- 1.8.0 ^ permalink raw reply related [flat|nested] 14+ messages in thread
* [PATCH V4 2/3] powerpc/85xx: Use common init functions for QE 2013-09-24 10:48 [PATCH V4 1/3] powerpc/85xx: Add QE common init functions Xie Xiaobo @ 2013-09-24 10:48 ` Xie Xiaobo 2013-09-24 10:48 ` [PATCH V4 3/3] powerpc/85xx: Add TWR-P1025 board support Xie Xiaobo 2013-09-24 23:13 ` [PATCH V4 1/3] powerpc/85xx: Add QE common init functions Scott Wood 2 siblings, 0 replies; 14+ messages in thread From: Xie Xiaobo @ 2013-09-24 10:48 UTC (permalink / raw) To: linuxppc-dev, scottwood; +Cc: Xie Xiaobo Use common init functions instead of the duplicated codes in some platforms with QUICC Engine. Signed-off-by: Xie Xiaobo <X.Xie@freescale.com> --- V4: new patch arch/powerpc/platforms/85xx/mpc85xx_mds.c | 55 ++----------------------------- arch/powerpc/platforms/85xx/mpc85xx_rdb.c | 36 ++------------------ 2 files changed, 4 insertions(+), 87 deletions(-) diff --git a/arch/powerpc/platforms/85xx/mpc85xx_mds.c b/arch/powerpc/platforms/85xx/mpc85xx_mds.c index a7b3621..da28d74 100644 --- a/arch/powerpc/platforms/85xx/mpc85xx_mds.c +++ b/arch/powerpc/platforms/85xx/mpc85xx_mds.c @@ -238,32 +238,7 @@ static void __init mpc85xx_mds_qe_init(void) { struct device_node *np; - np = of_find_compatible_node(NULL, NULL, "fsl,qe"); - if (!np) { - np = of_find_node_by_name(NULL, "qe"); - if (!np) - return; - } - - if (!of_device_is_available(np)) { - of_node_put(np); - return; - } - - qe_reset(); - of_node_put(np); - - np = of_find_node_by_name(NULL, "par_io"); - if (np) { - struct device_node *ucc; - - par_io_init(np); - of_node_put(np); - - for_each_node_by_name(ucc, "ucc") - par_io_of_config(ucc); - } - + mpc85xx_qe_init(); mpc85xx_mds_reset_ucc_phys(); if (machine_is(p1021_mds)) { @@ -293,34 +268,8 @@ static void __init mpc85xx_mds_qe_init(void) } } - -static void __init mpc85xx_mds_qeic_init(void) -{ - struct device_node *np; - - np = of_find_compatible_node(NULL, NULL, "fsl,qe"); - if (!of_device_is_available(np)) { - of_node_put(np); - return; - } - - np = of_find_compatible_node(NULL, NULL, "fsl,qe-ic"); - if (!np) { - np = of_find_node_by_type(NULL, "qeic"); - if (!np) - return; - } - - if (machine_is(p1021_mds)) - qe_ic_init(np, 0, qe_ic_cascade_low_mpic, - qe_ic_cascade_high_mpic); - else - qe_ic_init(np, 0, qe_ic_cascade_muxed_mpic, NULL); - of_node_put(np); -} #else static void __init mpc85xx_mds_qe_init(void) { } -static void __init mpc85xx_mds_qeic_init(void) { } #endif /* CONFIG_QUICC_ENGINE */ static void __init mpc85xx_mds_setup_arch(void) @@ -395,7 +344,7 @@ static void __init mpc85xx_mds_pic_init(void) BUG_ON(mpic == NULL); mpic_init(mpic); - mpc85xx_mds_qeic_init(); + mpc85xx_qe_pic_init(); } static int __init mpc85xx_mds_probe(void) diff --git a/arch/powerpc/platforms/85xx/mpc85xx_rdb.c b/arch/powerpc/platforms/85xx/mpc85xx_rdb.c index 53b6fb0..67d78e2 100644 --- a/arch/powerpc/platforms/85xx/mpc85xx_rdb.c +++ b/arch/powerpc/platforms/85xx/mpc85xx_rdb.c @@ -49,10 +49,6 @@ void __init mpc85xx_rdb_pic_init(void) struct mpic *mpic; unsigned long root = of_get_flat_dt_root(); -#ifdef CONFIG_QUICC_ENGINE - struct device_node *np; -#endif - if (of_flat_dt_is_compatible(root, "fsl,MPC85XXRDB-CAMP")) { mpic = mpic_alloc(NULL, 0, MPIC_NO_RESET | MPIC_BIG_ENDIAN | @@ -69,16 +65,8 @@ void __init mpc85xx_rdb_pic_init(void) mpic_init(mpic); #ifdef CONFIG_QUICC_ENGINE - np = of_find_compatible_node(NULL, NULL, "fsl,qe-ic"); - if (np) { - qe_ic_init(np, 0, qe_ic_cascade_low_mpic, - qe_ic_cascade_high_mpic); - of_node_put(np); - - } else - pr_err("%s: Could not find qe-ic node\n", __func__); + mpc85xx_qe_pic_init(); #endif - } /* @@ -98,26 +86,8 @@ static void __init mpc85xx_rdb_setup_arch(void) fsl_pci_assign_primary(); #ifdef CONFIG_QUICC_ENGINE - np = of_find_compatible_node(NULL, NULL, "fsl,qe"); - if (!np) { - pr_err("%s: Could not find Quicc Engine node\n", __func__); - goto qe_fail; - } + mpc85xx_qe_init(); - qe_reset(); - of_node_put(np); - - np = of_find_node_by_name(NULL, "par_io"); - if (np) { - struct device_node *ucc; - - par_io_init(np); - of_node_put(np); - - for_each_node_by_name(ucc, "ucc") - par_io_of_config(ucc); - - } #if defined(CONFIG_UCC_GETH) || defined(CONFIG_SERIAL_QE) if (machine_is(p1025_rdb)) { @@ -148,8 +118,6 @@ static void __init mpc85xx_rdb_setup_arch(void) } #endif - -qe_fail: #endif /* CONFIG_QUICC_ENGINE */ printk(KERN_INFO "MPC85xx RDB board from Freescale Semiconductor\n"); -- 1.8.0 ^ permalink raw reply related [flat|nested] 14+ messages in thread
* [PATCH V4 3/3] powerpc/85xx: Add TWR-P1025 board support 2013-09-24 10:48 [PATCH V4 1/3] powerpc/85xx: Add QE common init functions Xie Xiaobo 2013-09-24 10:48 ` [PATCH V4 2/3] powerpc/85xx: Use common init functions for QE Xie Xiaobo @ 2013-09-24 10:48 ` Xie Xiaobo 2013-09-24 23:22 ` Scott Wood 2013-09-24 23:13 ` [PATCH V4 1/3] powerpc/85xx: Add QE common init functions Scott Wood 2 siblings, 1 reply; 14+ messages in thread From: Xie Xiaobo @ 2013-09-24 10:48 UTC (permalink / raw) To: linuxppc-dev, scottwood; +Cc: Michael Johnston, Xie Xiaobo TWR-P1025 Overview ----------------- 512Mbyte DDR3 (on board DDR) 64MB Nor Flash eTSEC1: Connected to RGMII PHY AR8035 eTSEC3: Connected to RGMII PHY AR8035 Two USB2.0 Type A One microSD Card slot One mini-PCIe slot One mini-USB TypeB dual UART Signed-off-by: Michael Johnston <michael.johnston@freescale.com> Signed-off-by: Xie Xiaobo <X.Xie@freescale.com> --- Patch V4: Fix the mdio phy interrupt issue in dts Patch V3: fix pcie range issue in dts Patch V2: QE related init codes were factored out to a common file arch/powerpc/boot/dts/p1025twr.dtsi | 244 ++++++++++++++++++++++++++++++++ arch/powerpc/boot/dts/p1025twr_32b.dts | 135 ++++++++++++++++++ arch/powerpc/platforms/85xx/Kconfig | 6 + arch/powerpc/platforms/85xx/Makefile | 1 + arch/powerpc/platforms/85xx/twr_p102x.c | 142 +++++++++++++++++++ 5 files changed, 528 insertions(+) create mode 100644 arch/powerpc/boot/dts/p1025twr.dtsi create mode 100644 arch/powerpc/boot/dts/p1025twr_32b.dts create mode 100644 arch/powerpc/platforms/85xx/twr_p102x.c diff --git a/arch/powerpc/boot/dts/p1025twr.dtsi b/arch/powerpc/boot/dts/p1025twr.dtsi new file mode 100644 index 0000000..4b1d5f7 --- /dev/null +++ b/arch/powerpc/boot/dts/p1025twr.dtsi @@ -0,0 +1,244 @@ +/* + * P1025 TWR Device Tree Source stub (no addresses or top-level ranges) + * + * Copyright 2013 Freescale Semiconductor Inc. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * * Neither the name of Freescale Semiconductor nor the + * names of its contributors may be used to endorse or promote products + * derived from this software without specific prior written permission. + * + * + * ALTERNATIVELY, this software may be distributed under the terms of the + * GNU General Public License ("GPL") as published by the Free Software + * Foundation, either version 2 of that License or (at your option) any + * later version. + * + * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY + * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY + * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND + * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +/{ + aliases { + ethernet3 = &enet3; + ethernet4 = &enet4; + }; +}; + +&lbc { + nor@0,0 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "cfi-flash"; + reg = <0x0 0x0 0x4000000>; + bank-width = <2>; + device-width = <1>; + + partition@0 { + /* This location must not be altered */ + /* 256KB for Vitesse 7385 Switch firmware */ + reg = <0x0 0x00040000>; + label = "NOR Vitesse-7385 Firmware"; + read-only; + }; + + partition@40000 { + /* 256KB for DTB Image */ + reg = <0x00040000 0x00040000>; + label = "NOR DTB Image"; + }; + + partition@80000 { + /* 3.5 MB for Linux Kernel Image */ + reg = <0x00080000 0x00380000>; + label = "NOR Linux Kernel Image"; + }; + + partition@400000 { + /* 58.75MB for JFFS2 based Root file System */ + reg = <0x00400000 0x03ac0000>; + label = "NOR Root File System"; + }; + + partition@ec0000 { + /* This location must not be altered */ + /* 256KB for QE ucode firmware*/ + reg = <0x03ec0000 0x00040000>; + label = "NOR QE microcode firmware"; + read-only; + }; + + partition@f00000 { + /* This location must not be altered */ + /* 512KB for u-boot Bootloader Image */ + /* 512KB for u-boot Environment Variables */ + reg = <0x03f00000 0x00100000>; + label = "NOR U-Boot Image"; + read-only; + }; + }; + + /* CS2 for Display */ + ssd1289@2,0 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "ssd1289"; + reg = <0x2 0x0000 0x0002 + 0x2 0x0002 0x0002>; + }; + +}; + +&soc { + usb@22000 { + phy_type = "ulpi"; + }; + + mdio@24000 { + phy0: ethernet-phy@2 { + interrupt-parent = <&mpic>; + interrupts = <1 1 0 0>; + reg = <0x2>; + }; + + phy1: ethernet-phy@1 { + interrupt-parent = <&mpic>; + interrupts = <2 1 0 0>; + reg = <0x1>; + }; + + tbi0: tbi-phy@11 { + reg = <0x11>; + device_type = "tbi-phy"; + }; + }; + + mdio@25000 { + tbi1: tbi-phy@11 { + reg = <0x11>; + device_type = "tbi-phy"; + }; + }; + + mdio@26000 { + tbi2: tbi-phy@11 { + reg = <0x11>; + device_type = "tbi-phy"; + }; + }; + + enet0: ethernet@b0000 { + phy-handle = <&phy0>; + phy-connection-type = "rgmii-id"; + + }; + + enet1: ethernet@b1000 { + status = "disabled"; + }; + + enet2: ethernet@b2000 { + phy-handle = <&phy1>; + phy-connection-type = "rgmii-id"; + }; + + par_io@e0100 { + #address-cells = <1>; + #size-cells = <1>; + reg = <0xe0100 0x60>; + ranges = <0x0 0xe0100 0x60>; + device_type = "par_io"; + num-ports = <3>; + pio1: ucc_pin@01 { + pio-map = < + /* port pin dir open_drain assignment has_irq */ + 0x1 0x13 0x1 0x0 0x1 0x0 /* QE_MUX_MDC */ + 0x1 0x14 0x3 0x0 0x1 0x0 /* QE_MUX_MDIO */ + 0x0 0x17 0x2 0x0 0x2 0x0 /* CLK12 */ + 0x0 0x18 0x2 0x0 0x1 0x0 /* CLK9 */ + 0x0 0x7 0x1 0x0 0x2 0x0 /* ENET1_TXD0_SER1_TXD0 */ + 0x0 0x9 0x1 0x0 0x2 0x0 /* ENET1_TXD1_SER1_TXD1 */ + 0x0 0xb 0x1 0x0 0x2 0x0 /* ENET1_TXD2_SER1_TXD2 */ + 0x0 0xc 0x1 0x0 0x2 0x0 /* ENET1_TXD3_SER1_TXD3 */ + 0x0 0x6 0x2 0x0 0x2 0x0 /* ENET1_RXD0_SER1_RXD0 */ + 0x0 0xa 0x2 0x0 0x2 0x0 /* ENET1_RXD1_SER1_RXD1 */ + 0x0 0xe 0x2 0x0 0x2 0x0 /* ENET1_RXD2_SER1_RXD2 */ + 0x0 0xf 0x2 0x0 0x2 0x0 /* ENET1_RXD3_SER1_RXD3 */ + 0x0 0x5 0x1 0x0 0x2 0x0 /* ENET1_TX_EN_SER1_RTS_B */ + 0x0 0xd 0x1 0x0 0x2 0x0 /* ENET1_TX_ER */ + 0x0 0x4 0x2 0x0 0x2 0x0 /* ENET1_RX_DV_SER1_CTS_B */ + 0x0 0x8 0x2 0x0 0x2 0x0 /* ENET1_RX_ER_SER1_CD_B */ + 0x0 0x11 0x2 0x0 0x2 0x0 /* ENET1_CRS */ + 0x0 0x10 0x2 0x0 0x2 0x0>; /* ENET1_COL */ + }; + + pio2: ucc_pin@02 { + pio-map = < + /* port pin dir open_drain assignment has_irq */ + 0x1 0x13 0x1 0x0 0x1 0x0 /* QE_MUX_MDC */ + 0x1 0x14 0x3 0x0 0x1 0x0 /* QE_MUX_MDIO */ + 0x1 0xb 0x2 0x0 0x1 0x0 /* CLK13 */ + 0x1 0x7 0x1 0x0 0x2 0x0 /* ENET5_TXD0_SER5_TXD0 */ + 0x1 0xa 0x1 0x0 0x2 0x0 /* ENET5_TXD1_SER5_TXD1 */ + 0x1 0x6 0x2 0x0 0x2 0x0 /* ENET5_RXD0_SER5_RXD0 */ + 0x1 0x9 0x2 0x0 0x2 0x0 /* ENET5_RXD1_SER5_RXD1 */ + 0x1 0x5 0x1 0x0 0x2 0x0 /* ENET5_TX_EN_SER5_RTS_B */ + 0x1 0x4 0x2 0x0 0x2 0x0 /* ENET5_RX_DV_SER5_CTS_B */ + 0x1 0x8 0x2 0x0 0x2 0x0>; /* ENET5_RX_ER_SER5_CD_B */ + }; + + pio3: ucc_pin@03 { + pio-map = < + /* port pin dir open_drain assignment has_irq */ + 0x0 0x16 0x2 0x0 0x2 0x0 /* SER7_CD_B*/ + 0x0 0x12 0x2 0x0 0x2 0x0 /* SER7_CTS_B*/ + 0x0 0x13 0x1 0x0 0x2 0x0 /* SER7_RTS_B*/ + 0x0 0x14 0x2 0x0 0x2 0x0 /* SER7_RXD0*/ + 0x0 0x15 0x1 0x0 0x2 0x0>; /* SER7_TXD0*/ + }; + + pio4: ucc_pin@04 { + pio-map = < + /* port pin dir open_drain assignment has_irq */ + 0x1 0x0 0x2 0x0 0x2 0x0 /* SER3_CD_B*/ + 0x0 0x1c 0x2 0x0 0x2 0x0 /* SER3_CTS_B*/ + 0x0 0x1d 0x1 0x0 0x2 0x0 /* SER3_RTS_B*/ + 0x0 0x1e 0x2 0x0 0x2 0x0 /* SER3_RXD0*/ + 0x0 0x1f 0x1 0x0 0x2 0x0>; /* SER3_TXD0*/ + }; + }; +}; + +&qe { + serial2: ucc@2600 { + device_type = "serial"; + compatible = "ucc_uart"; + port-number = <0>; + rx-clock-name = "brg6"; + tx-clock-name = "brg6"; + pio-handle = <&pio3>; + }; + + serial3: ucc@2200 { + device_type = "serial"; + compatible = "ucc_uart"; + port-number = <1>; + rx-clock-name = "brg2"; + tx-clock-name = "brg2"; + pio-handle = <&pio4>; + }; +}; diff --git a/arch/powerpc/boot/dts/p1025twr_32b.dts b/arch/powerpc/boot/dts/p1025twr_32b.dts new file mode 100644 index 0000000..ccb173f --- /dev/null +++ b/arch/powerpc/boot/dts/p1025twr_32b.dts @@ -0,0 +1,135 @@ +/* + * P1025 TWR Device Tree Source (32-bit address map) + * + * Copyright 2013 Freescale Semiconductor Inc. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * * Neither the name of Freescale Semiconductor nor the + * names of its contributors may be used to endorse or promote products + * derived from this software without specific prior written permission. + * + * + * ALTERNATIVELY, this software may be distributed under the terms of the + * GNU General Public License ("GPL") as published by the Free Software + * Foundation, either version 2 of that License or (at your option) any + * later version. + * + * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY + * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY + * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND + * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +/include/ "fsl/p1021si-pre.dtsi" +/ { + model = "fsl,P1025"; + compatible = "fsl,TWR-P1025"; + + memory { + device_type = "memory"; + }; + + lbc: localbus@ffe05000 { + reg = <0 0xffe05000 0 0x1000>; + + /* NOR Flash and SSD1289 */ + ranges = <0x0 0x0 0x0 0xec000000 0x04000000 + 0x2 0x0 0x0 0xe0000000 0x00020000>; + }; + + soc: soc@ffe00000 { + ranges = <0x0 0x0 0xffe00000 0x100000>; + }; + + pci0: pcie@ffe09000 { + ranges = <0x2000000 0x0 0xa0000000 0 0xa0000000 0x0 0x20000000 + 0x1000000 0x0 0x00000000 0 0xffc10000 0x0 0x10000>; + reg = <0 0xffe09000 0 0x1000>; + pcie@0 { + ranges = <0x2000000 0x0 0xa0000000 + 0x2000000 0x0 0xa0000000 + 0x0 0x20000000 + + 0x1000000 0x0 0x0 + 0x1000000 0x0 0x0 + 0x0 0x100000>; + }; + }; + + pci1: pcie@ffe0a000 { + reg = <0 0xffe0a000 0 0x1000>; + ranges = <0x2000000 0x0 0x80000000 0 0x80000000 0x0 0x20000000 + 0x1000000 0x0 0x00000000 0 0xffc00000 0x0 0x10000>; + pcie@0 { + ranges = <0x2000000 0x0 0x80000000 + 0x2000000 0x0 0x80000000 + 0x0 0x20000000 + + 0x1000000 0x0 0x0 + 0x1000000 0x0 0x0 + 0x0 0x100000>; + }; + }; + + qe: qe@ffe80000 { + ranges = <0x0 0x0 0xffe80000 0x40000>; + reg = <0 0xffe80000 0 0x480>; + brg-frequency = <0>; + bus-frequency = <0>; + status = "disabled"; /* no firmware loaded */ + + enet3: ucc@2000 { + device_type = "network"; + compatible = "ucc_geth"; + rx-clock-name = "clk12"; + tx-clock-name = "clk9"; + pio-handle = <&pio1>; + phy-handle = <&qe_phy0>; + phy-connection-type = "mii"; + }; + + mdio@2120 { + qe_phy0: ethernet-phy@18 { + interrupt-parent = <&mpic>; + interrupts = <4 1 0 0>; + reg = <0x18>; + device_type = "ethernet-phy"; + }; + qe_phy1: ethernet-phy@19 { + interrupt-parent = <&mpic>; + interrupts = <5 1 0 0>; + reg = <0x19>; + device_type = "ethernet-phy"; + }; + tbi-phy@11 { + reg = <0x11>; + device_type = "tbi-phy"; + }; + }; + + enet4: ucc@2400 { + device_type = "network"; + compatible = "ucc_geth"; + rx-clock-name = "none"; + tx-clock-name = "clk13"; + pio-handle = <&pio2>; + phy-handle = <&qe_phy1>; + phy-connection-type = "rmii"; + }; + }; +}; + +/include/ "p1025twr.dtsi" +/include/ "fsl/p1021si-post.dtsi" diff --git a/arch/powerpc/platforms/85xx/Kconfig b/arch/powerpc/platforms/85xx/Kconfig index de2eb93..b1a7d0a 100644 --- a/arch/powerpc/platforms/85xx/Kconfig +++ b/arch/powerpc/platforms/85xx/Kconfig @@ -123,6 +123,12 @@ config P1023_RDS help This option enables support for the P1023 RDS and RDB boards +config TWR_P102x + bool "Freescale TWR-P102x" + select DEFAULT_UIMAGE + help + This option enables support for the TWR-P1025 board. + config SOCRATES bool "Socrates" select DEFAULT_UIMAGE diff --git a/arch/powerpc/platforms/85xx/Makefile b/arch/powerpc/platforms/85xx/Makefile index 53c9f75..228c4dd 100644 --- a/arch/powerpc/platforms/85xx/Makefile +++ b/arch/powerpc/platforms/85xx/Makefile @@ -18,6 +18,7 @@ obj-$(CONFIG_P1010_RDB) += p1010rdb.o obj-$(CONFIG_P1022_DS) += p1022_ds.o obj-$(CONFIG_P1022_RDK) += p1022_rdk.o obj-$(CONFIG_P1023_RDS) += p1023_rds.o +obj-$(CONFIG_TWR_P102x) += twr_p102x.o obj-$(CONFIG_P2041_RDB) += p2041_rdb.o corenet_ds.o obj-$(CONFIG_P3041_DS) += p3041_ds.o corenet_ds.o obj-$(CONFIG_P4080_DS) += p4080_ds.o corenet_ds.o diff --git a/arch/powerpc/platforms/85xx/twr_p102x.c b/arch/powerpc/platforms/85xx/twr_p102x.c new file mode 100644 index 0000000..8ba3b25 --- /dev/null +++ b/arch/powerpc/platforms/85xx/twr_p102x.c @@ -0,0 +1,142 @@ +/* + * Copyright 2010-2011, 2013 Freescale Semiconductor, Inc. + * + * Author: Michael Johnston <michael.johnston@freescale.com> + * + * Description: + * TWR-P102x Board Setup + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License as published by the + * Free Software Foundation; either version 2 of the License, or (at your + * option) any later version. + */ + +#include <linux/kernel.h> +#include <linux/init.h> +#include <linux/errno.h> +#include <linux/pci.h> +#include <linux/of_platform.h> + +#include <asm/pci-bridge.h> +#include <asm/udbg.h> +#include <asm/mpic.h> +#include <asm/qe.h> +#include <asm/qe_ic.h> +#include <asm/fsl_guts.h> + +#include <sysdev/fsl_soc.h> +#include <sysdev/fsl_pci.h> +#include "smp.h" + +#include "mpc85xx.h" + +static void __init twr_p1025_pic_init(void) +{ + struct mpic *mpic; + + mpic = mpic_alloc(NULL, 0, MPIC_BIG_ENDIAN | + MPIC_SINGLE_DEST_CPU, + 0, 256, " OpenPIC "); + + BUG_ON(mpic == NULL); + mpic_init(mpic); + +#ifdef CONFIG_QUICC_ENGINE + mpc85xx_qe_pic_init(); +#endif +} + +/* ************************************************************************ + * + * Setup the architecture + * + */ +static void __init twr_p1025_setup_arch(void) +{ +#ifdef CONFIG_QUICC_ENGINE + struct device_node *np; +#endif + + if (ppc_md.progress) + ppc_md.progress("twr_p1025_setup_arch()", 0); + + mpc85xx_smp_init(); + + fsl_pci_assign_primary(); + +#ifdef CONFIG_QUICC_ENGINE + mpc85xx_qe_init(); + +#if defined(CONFIG_UCC_GETH) || defined(CONFIG_SERIAL_QE) + if (machine_is(twr_p1025)) { + struct ccsr_guts __iomem *guts; + + np = of_find_node_by_name(NULL, "global-utilities"); + if (np) { + guts = of_iomap(np, 0); + if (!guts) + pr_err("twr_p1025: could not map" + "global utilities register\n"); + else { + /* P1025 has pins muxed for QE and other functions. To + * enable QE UEC mode, we need to set bit QE0 for UCC1 + * in Eth mode, QE0 and QE3 for UCC5 in Eth mode, QE9 + * and QE12 for QE MII management signals in PMUXCR + * register. + */ + + printk(KERN_INFO "P1025 pinmux configured for QE\n"); + + /* Set QE mux bits in PMUXCR */ + setbits32(&guts->pmuxcr, MPC85xx_PMUXCR_QE(0) | + MPC85xx_PMUXCR_QE(3) | + MPC85xx_PMUXCR_QE(9) | + MPC85xx_PMUXCR_QE(12)); + iounmap(guts); + +#if defined(CONFIG_SERIAL_QE) + /* On P1025TWR board, the UCC7 acted as UART port. + * However, The UCC7's CTS pin is low level in default, + * it will impact the transmission in full duplex + * communication. So disable the Flow control pin PA18. + * The UCC7 UART just can use RXD and TXD pins. + */ + par_io_config_pin(0, 18, 0, 0, 0, 0); +#endif + /* Drive PB29 to CPLD low - CPLD will then change + * muxing from LBC to QE */ + par_io_config_pin(1, 29, 1, 0, 0, 0); + par_io_data_set(1, 29, 0); + } + of_node_put(np); + } + } +#endif +#endif /* CONFIG_QUICC_ENGINE */ + + printk(KERN_INFO "TWR-P1025 board from Freescale Semiconductor\n"); +} + +machine_arch_initcall(twr_p1025, mpc85xx_common_publish_devices); + +static int __init twr_p1025_probe(void) +{ + unsigned long root = of_get_flat_dt_root(); + + return of_flat_dt_is_compatible(root, "fsl,TWR-P1025"); +} + +define_machine(twr_p1025) { + .name = "TWR-P1025", + .probe = twr_p1025_probe, + .setup_arch = twr_p1025_setup_arch, + .init_IRQ = twr_p1025_pic_init, +#ifdef CONFIG_PCI + .pcibios_fixup_bus = fsl_pcibios_fixup_bus, +#endif + .get_irq = mpic_get_irq, + .restart = fsl_rstcr_restart, + .calibrate_decr = generic_calibrate_decr, + .progress = udbg_progress, +}; -- 1.8.0 ^ permalink raw reply related [flat|nested] 14+ messages in thread
* Re: [PATCH V4 3/3] powerpc/85xx: Add TWR-P1025 board support 2013-09-24 10:48 ` [PATCH V4 3/3] powerpc/85xx: Add TWR-P1025 board support Xie Xiaobo @ 2013-09-24 23:22 ` Scott Wood 2013-09-25 9:50 ` Xie Xiaobo-R63061 0 siblings, 1 reply; 14+ messages in thread From: Scott Wood @ 2013-09-24 23:22 UTC (permalink / raw) To: Xie Xiaobo; +Cc: linuxppc-dev, Michael Johnston On Tue, 2013-09-24 at 18:48 +0800, Xie Xiaobo wrote: > + partition@80000 { > + /* 3.5 MB for Linux Kernel Image */ > + reg = <0x00080000 0x00380000>; > + label = "NOR Linux Kernel Image"; > + }; Is this enough? > + partition@400000 { > + /* 58.75MB for JFFS2 based Root file System */ > + reg = <0x00400000 0x03ac0000>; > + label = "NOR Root File System"; > + }; Don't specify jffs2. > + /* CS2 for Display */ > + ssd1289@2,0 { > + #address-cells = <1>; > + #size-cells = <1>; > + compatible = "ssd1289"; > + reg = <0x2 0x0000 0x0002 > + 0x2 0x0002 0x0002>; > + }; Node names should be generic. What does ssd1289 do? If this is actually the display device, then it should be called "display@2,0". How about a vendor prefix on that compatible? Why #address-cells/#size-cells despite no child nodes? Where is a binding that says what each of those two reg resources mean? > diff --git a/arch/powerpc/boot/dts/p1025twr_32b.dts b/arch/powerpc/boot/dts/p1025twr_32b.dts > new file mode 100644 > index 0000000..ccb173f > --- /dev/null > +++ b/arch/powerpc/boot/dts/p1025twr_32b.dts > @@ -0,0 +1,135 @@ > +/* > + * P1025 TWR Device Tree Source (32-bit address map) > + * > + * Copyright 2013 Freescale Semiconductor Inc. > + * > + * Redistribution and use in source and binary forms, with or without > + * modification, are permitted provided that the following conditions are met: > + * * Redistributions of source code must retain the above copyright > + * notice, this list of conditions and the following disclaimer. > + * * Redistributions in binary form must reproduce the above copyright > + * notice, this list of conditions and the following disclaimer in the > + * documentation and/or other materials provided with the distribution. > + * * Neither the name of Freescale Semiconductor nor the > + * names of its contributors may be used to endorse or promote products > + * derived from this software without specific prior written permission. > + * > + * > + * ALTERNATIVELY, this software may be distributed under the terms of the > + * GNU General Public License ("GPL") as published by the Free Software > + * Foundation, either version 2 of that License or (at your option) any > + * later version. > + * > + * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY > + * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED > + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE > + * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY > + * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES > + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; > + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND > + * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT > + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS > + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. > + */ > + > +/include/ "fsl/p1021si-pre.dtsi" > +/ { > + model = "fsl,P1025"; > + compatible = "fsl,TWR-P1025"; > + > + memory { > + device_type = "memory"; > + }; > + > + lbc: localbus@ffe05000 { > + reg = <0 0xffe05000 0 0x1000>; > + > + /* NOR Flash and SSD1289 */ > + ranges = <0x0 0x0 0x0 0xec000000 0x04000000 > + 0x2 0x0 0x0 0xe0000000 0x00020000>; > + }; > + > + soc: soc@ffe00000 { > + ranges = <0x0 0x0 0xffe00000 0x100000>; > + }; > + > + pci0: pcie@ffe09000 { > + ranges = <0x2000000 0x0 0xa0000000 0 0xa0000000 0x0 0x20000000 > + 0x1000000 0x0 0x00000000 0 0xffc10000 0x0 0x10000>; > + reg = <0 0xffe09000 0 0x1000>; > + pcie@0 { > + ranges = <0x2000000 0x0 0xa0000000 > + 0x2000000 0x0 0xa0000000 > + 0x0 0x20000000 > + > + 0x1000000 0x0 0x0 > + 0x1000000 0x0 0x0 > + 0x0 0x100000>; > + }; > + }; > + > + pci1: pcie@ffe0a000 { > + reg = <0 0xffe0a000 0 0x1000>; > + ranges = <0x2000000 0x0 0x80000000 0 0x80000000 0x0 0x20000000 > + 0x1000000 0x0 0x00000000 0 0xffc00000 0x0 0x10000>; > + pcie@0 { > + ranges = <0x2000000 0x0 0x80000000 > + 0x2000000 0x0 0x80000000 > + 0x0 0x20000000 > + > + 0x1000000 0x0 0x0 > + 0x1000000 0x0 0x0 > + 0x0 0x100000>; > + }; > + }; > + > + qe: qe@ffe80000 { > + ranges = <0x0 0x0 0xffe80000 0x40000>; > + reg = <0 0xffe80000 0 0x480>; > + brg-frequency = <0>; > + bus-frequency = <0>; > + status = "disabled"; /* no firmware loaded */ > + > + enet3: ucc@2000 { > + device_type = "network"; > + compatible = "ucc_geth"; > + rx-clock-name = "clk12"; > + tx-clock-name = "clk9"; > + pio-handle = <&pio1>; > + phy-handle = <&qe_phy0>; > + phy-connection-type = "mii"; > + }; > + > + mdio@2120 { > + qe_phy0: ethernet-phy@18 { > + interrupt-parent = <&mpic>; > + interrupts = <4 1 0 0>; > + reg = <0x18>; > + device_type = "ethernet-phy"; > + }; > + qe_phy1: ethernet-phy@19 { > + interrupt-parent = <&mpic>; > + interrupts = <5 1 0 0>; > + reg = <0x19>; > + device_type = "ethernet-phy"; > + }; > + tbi-phy@11 { > + reg = <0x11>; > + device_type = "tbi-phy"; > + }; > + }; > + > + enet4: ucc@2400 { > + device_type = "network"; > + compatible = "ucc_geth"; > + rx-clock-name = "none"; > + tx-clock-name = "clk13"; > + pio-handle = <&pio2>; > + phy-handle = <&qe_phy1>; > + phy-connection-type = "rmii"; > + }; > + }; > +}; Don't duplicate all this just for 32/36 bit. Use a dtsi for (e.g.) the contents of the QE node. Is there a strong need to support both 32 and 36 bit in the first place? > +/* ************************************************************************ > + * > + * Setup the architecture > + * > + */ > +static void __init twr_p1025_setup_arch(void) > +{ > +#ifdef CONFIG_QUICC_ENGINE > + struct device_node *np; > +#endif > + > + if (ppc_md.progress) > + ppc_md.progress("twr_p1025_setup_arch()", 0); > + > + mpc85xx_smp_init(); > + > + fsl_pci_assign_primary(); > + > +#ifdef CONFIG_QUICC_ENGINE > + mpc85xx_qe_init(); > + > +#if defined(CONFIG_UCC_GETH) || defined(CONFIG_SERIAL_QE) > + if (machine_is(twr_p1025)) { > + struct ccsr_guts __iomem *guts; > + > + np = of_find_node_by_name(NULL, "global-utilities"); Look for it by compatible. > + if (np) { > + guts = of_iomap(np, 0); > + if (!guts) > + pr_err("twr_p1025: could not map" > + "global utilities register\n"); Don't linewrap printed string constants (this is an exception to the 80-column rule). > + else { > + /* P1025 has pins muxed for QE and other functions. To > + * enable QE UEC mode, we need to set bit QE0 for UCC1 > + * in Eth mode, QE0 and QE3 for UCC5 in Eth mode, QE9 > + * and QE12 for QE MII management signals in PMUXCR > + * register. > + */ > + > + printk(KERN_INFO "P1025 pinmux configured for QE\n"); Bad indentation, and use pr_info() (or better, just remove it; it's implied by the absence of the error on the other branch of the if). > + > + /* Set QE mux bits in PMUXCR */ > + setbits32(&guts->pmuxcr, MPC85xx_PMUXCR_QE(0) | > + MPC85xx_PMUXCR_QE(3) | > + MPC85xx_PMUXCR_QE(9) | > + MPC85xx_PMUXCR_QE(12)); > + iounmap(guts); > + > +#if defined(CONFIG_SERIAL_QE) > + /* On P1025TWR board, the UCC7 acted as UART port. > + * However, The UCC7's CTS pin is low level in default, > + * it will impact the transmission in full duplex > + * communication. So disable the Flow control pin PA18. > + * The UCC7 UART just can use RXD and TXD pins. > + */ > + par_io_config_pin(0, 18, 0, 0, 0, 0); > +#endif Any reason not to do this unconditionally? -Scott ^ permalink raw reply [flat|nested] 14+ messages in thread
* RE: [PATCH V4 3/3] powerpc/85xx: Add TWR-P1025 board support 2013-09-24 23:22 ` Scott Wood @ 2013-09-25 9:50 ` Xie Xiaobo-R63061 2013-09-25 23:09 ` Scott Wood 2013-09-27 17:03 ` Scott Wood 0 siblings, 2 replies; 14+ messages in thread From: Xie Xiaobo-R63061 @ 2013-09-25 9:50 UTC (permalink / raw) To: Wood Scott-B07421; +Cc: Johnston Michael-R49610, linuxppc-dev@lists.ozlabs.org SGkgU2NvdHQsDQoNClNlZSB0aGUgcmVwbHkgaW5saW5lLg0KDQo+IC0tLS0tT3JpZ2luYWwgTWVz c2FnZS0tLS0tDQo+IEZyb206IFdvb2QgU2NvdHQtQjA3NDIxDQo+IFNlbnQ6IFdlZG5lc2RheSwg U2VwdGVtYmVyIDI1LCAyMDEzIDc6MjIgQU0NCj4gVG86IFhpZSBYaWFvYm8tUjYzMDYxDQo+IENj OiBsaW51eHBwYy1kZXZAbGlzdHMub3psYWJzLm9yZzsgSm9obnN0b24gTWljaGFlbC1SNDk2MTAN Cj4gU3ViamVjdDogUmU6IFtQQVRDSCBWNCAzLzNdIHBvd2VycGMvODV4eDogQWRkIFRXUi1QMTAy NSBib2FyZCBzdXBwb3J0DQo+IA0KPiBPbiBUdWUsIDIwMTMtMDktMjQgYXQgMTg6NDggKzA4MDAs IFhpZSBYaWFvYm8gd3JvdGU6DQo+ID4gKwkJcGFydGl0aW9uQDgwMDAwIHsNCj4gPiArCQkJLyog My41IE1CIGZvciBMaW51eCBLZXJuZWwgSW1hZ2UgKi8NCj4gPiArCQkJcmVnID0gPDB4MDAwODAw MDAgMHgwMDM4MDAwMD47DQo+ID4gKwkJCWxhYmVsID0gIk5PUiBMaW51eCBLZXJuZWwgSW1hZ2Ui Ow0KPiA+ICsJCX07DQo+IA0KPiBJcyB0aGlzIGVub3VnaD8NCg0KSSB3aWxsIGVubGFyZ2UgaXQg dG8gNk1CLg0KIA0KPiANCj4gPiArCQlwYXJ0aXRpb25ANDAwMDAwIHsNCj4gPiArCQkJLyogNTgu NzVNQiBmb3IgSkZGUzIgYmFzZWQgUm9vdCBmaWxlIFN5c3RlbSAqLw0KPiA+ICsJCQlyZWcgPSA8 MHgwMDQwMDAwMCAweDAzYWMwMDAwPjsNCj4gPiArCQkJbGFiZWwgPSAiTk9SIFJvb3QgRmlsZSBT eXN0ZW0iOw0KPiA+ICsJCX07DQo+IA0KPiBEb24ndCBzcGVjaWZ5IGpmZnMyLg0KDQpPSywgSSB3 aWxsIHJlbW92ZSAiamZmczIiDQoNCj4gDQo+ID4gKwkvKiBDUzIgZm9yIERpc3BsYXkgKi8NCj4g PiArCXNzZDEyODlAMiwwIHsNCj4gPiArCQkjYWRkcmVzcy1jZWxscyA9IDwxPjsNCj4gPiArCQkj c2l6ZS1jZWxscyA9IDwxPjsNCj4gPiArCQljb21wYXRpYmxlID0gInNzZDEyODkiOw0KPiA+ICsJ CXJlZyA9IDwweDIgMHgwMDAwIDB4MDAwMg0KPiA+ICsJCSAgICAgICAweDIgMHgwMDAyIDB4MDAw Mj47DQo+ID4gKwl9Ow0KPiANCj4gTm9kZSBuYW1lcyBzaG91bGQgYmUgZ2VuZXJpYy4gIFdoYXQg ZG9lcyBzc2QxMjg5IGRvPyAgSWYgdGhpcyBpcyBhY3R1YWxseQ0KPiB0aGUgZGlzcGxheSBkZXZp Y2UsIHRoZW4gaXQgc2hvdWxkIGJlIGNhbGxlZCAiZGlzcGxheUAyLDAiLg0KDQpPSy4gVGhlIHNz ZDEyODkgaXMgYSBMQ0QgY29udHJvbGxlci4NCg0KPiANCj4gSG93IGFib3V0IGEgdmVuZG9yIHBy ZWZpeCBvbiB0aGF0IGNvbXBhdGlibGU/ICBXaHkgI2FkZHJlc3MtY2VsbHMvI3NpemUtDQo+IGNl bGxzIGRlc3BpdGUgbm8gY2hpbGQgbm9kZXM/ICBXaGVyZSBpcyBhIGJpbmRpbmcgdGhhdCBzYXlz IHdoYXQgZWFjaCBvZg0KPiB0aG9zZSB0d28gcmVnIHJlc291cmNlcyBtZWFuPw0KDQpJIHdpbGwg YWRkIHRoZSB2ZW5kb3IgcHJlZml4LiBJIHJldmlldyB0aGUgc3NkMTI4OSBkcml2ZXIsIGFuZCB0 aGUgI2FkZHJlc3MtY2VsbHMvI3NpemUtY2VsbHMgd2VyZSB1bi11c2VkLiBJIHdpbGwgcmVtb3Zl IHRoZW0uDQoNCj4gDQo+ID4gZGlmZiAtLWdpdCBhL2FyY2gvcG93ZXJwYy9ib290L2R0cy9wMTAy NXR3cl8zMmIuZHRzDQo+ID4gYi9hcmNoL3Bvd2VycGMvYm9vdC9kdHMvcDEwMjV0d3JfMzJiLmR0 cw0KPiA+IG5ldyBmaWxlIG1vZGUgMTAwNjQ0DQo+ID4gaW5kZXggMDAwMDAwMC4uY2NiMTczZg0K PiA+IC0tLSAvZGV2L251bGwNCj4gPiArKysgYi9hcmNoL3Bvd2VycGMvYm9vdC9kdHMvcDEwMjV0 d3JfMzJiLmR0cw0KPiA+IEBAIC0wLDAgKzEsMTM1IEBADQo+ID4gKy8qDQo+ID4gKyAqIFAxMDI1 IFRXUiBEZXZpY2UgVHJlZSBTb3VyY2UgKDMyLWJpdCBhZGRyZXNzIG1hcCkNCj4gPiArICoNCj4g PiArICogQ29weXJpZ2h0IDIwMTMgRnJlZXNjYWxlIFNlbWljb25kdWN0b3IgSW5jLg0KPiA+ICsg Kg0KPiA+ICsgKiBSZWRpc3RyaWJ1dGlvbiBhbmQgdXNlIGluIHNvdXJjZSBhbmQgYmluYXJ5IGZv cm1zLCB3aXRoIG9yIHdpdGhvdXQNCj4gPiArICogbW9kaWZpY2F0aW9uLCBhcmUgcGVybWl0dGVk IHByb3ZpZGVkIHRoYXQgdGhlIGZvbGxvd2luZyBjb25kaXRpb25zDQo+IGFyZSBtZXQ6DQo+ID4g KyAqICAgICAqIFJlZGlzdHJpYnV0aW9ucyBvZiBzb3VyY2UgY29kZSBtdXN0IHJldGFpbiB0aGUg YWJvdmUNCj4gY29weXJpZ2h0DQo+ID4gKyAqICAgICAgIG5vdGljZSwgdGhpcyBsaXN0IG9mIGNv bmRpdGlvbnMgYW5kIHRoZSBmb2xsb3dpbmcgZGlzY2xhaW1lci4NCj4gPiArICogICAgICogUmVk aXN0cmlidXRpb25zIGluIGJpbmFyeSBmb3JtIG11c3QgcmVwcm9kdWNlIHRoZSBhYm92ZQ0KPiBj b3B5cmlnaHQNCj4gPiArICogICAgICAgbm90aWNlLCB0aGlzIGxpc3Qgb2YgY29uZGl0aW9ucyBh bmQgdGhlIGZvbGxvd2luZyBkaXNjbGFpbWVyDQo+IGluIHRoZQ0KPiA+ICsgKiAgICAgICBkb2N1 bWVudGF0aW9uIGFuZC9vciBvdGhlciBtYXRlcmlhbHMgcHJvdmlkZWQgd2l0aCB0aGUNCj4gZGlz dHJpYnV0aW9uLg0KPiA+ICsgKiAgICAgKiBOZWl0aGVyIHRoZSBuYW1lIG9mIEZyZWVzY2FsZSBT ZW1pY29uZHVjdG9yIG5vciB0aGUNCj4gPiArICogICAgICAgbmFtZXMgb2YgaXRzIGNvbnRyaWJ1 dG9ycyBtYXkgYmUgdXNlZCB0byBlbmRvcnNlIG9yIHByb21vdGUNCj4gcHJvZHVjdHMNCj4gPiAr ICogICAgICAgZGVyaXZlZCBmcm9tIHRoaXMgc29mdHdhcmUgd2l0aG91dCBzcGVjaWZpYyBwcmlv ciB3cml0dGVuDQo+IHBlcm1pc3Npb24uDQo+ID4gKyAqDQo+ID4gKyAqDQo+ID4gKyAqIEFMVEVS TkFUSVZFTFksIHRoaXMgc29mdHdhcmUgbWF5IGJlIGRpc3RyaWJ1dGVkIHVuZGVyIHRoZSB0ZXJt cyBvZg0KPiA+ICt0aGUNCj4gPiArICogR05VIEdlbmVyYWwgUHVibGljIExpY2Vuc2UgKCJHUEwi KSBhcyBwdWJsaXNoZWQgYnkgdGhlIEZyZWUNCj4gPiArU29mdHdhcmUNCj4gPiArICogRm91bmRh dGlvbiwgZWl0aGVyIHZlcnNpb24gMiBvZiB0aGF0IExpY2Vuc2Ugb3IgKGF0IHlvdXIgb3B0aW9u KQ0KPiA+ICthbnkNCj4gPiArICogbGF0ZXIgdmVyc2lvbi4NCj4gPiArICoNCj4gPiArICogVEhJ UyBTT0ZUV0FSRSBJUyBQUk9WSURFRCBCWSBGcmVlc2NhbGUgU2VtaWNvbmR1Y3RvciBgYEFTIElT JycgQU5EDQo+ID4gK0FOWQ0KPiA+ICsgKiBFWFBSRVNTIE9SIElNUExJRUQgV0FSUkFOVElFUywg SU5DTFVESU5HLCBCVVQgTk9UIExJTUlURUQgVE8sIFRIRQ0KPiA+ICtJTVBMSUVEDQo+ID4gKyAq IFdBUlJBTlRJRVMgT0YgTUVSQ0hBTlRBQklMSVRZIEFORCBGSVRORVNTIEZPUiBBIFBBUlRJQ1VM QVIgUFVSUE9TRQ0KPiA+ICtBUkUNCj4gPiArICogRElTQ0xBSU1FRC4gSU4gTk8gRVZFTlQgU0hB TEwgRnJlZXNjYWxlIFNlbWljb25kdWN0b3IgQkUgTElBQkxFDQo+ID4gK0ZPUiBBTlkNCj4gPiAr ICogRElSRUNULCBJTkRJUkVDVCwgSU5DSURFTlRBTCwgU1BFQ0lBTCwgRVhFTVBMQVJZLCBPUiBD T05TRVFVRU5USUFMDQo+ID4gK0RBTUFHRVMNCj4gPiArICogKElOQ0xVRElORywgQlVUIE5PVCBM SU1JVEVEIFRPLCBQUk9DVVJFTUVOVCBPRiBTVUJTVElUVVRFIEdPT0RTIE9SDQo+ID4gK1NFUlZJ Q0VTOw0KPiA+ICsgKiBMT1NTIE9GIFVTRSwgREFUQSwgT1IgUFJPRklUUzsgT1IgQlVTSU5FU1Mg SU5URVJSVVBUSU9OKSBIT1dFVkVSDQo+ID4gK0NBVVNFRCBBTkQNCj4gPiArICogT04gQU5ZIFRI RU9SWSBPRiBMSUFCSUxJVFksIFdIRVRIRVIgSU4gQ09OVFJBQ1QsIFNUUklDVCBMSUFCSUxJVFks DQo+ID4gK09SIFRPUlQNCj4gPiArICogKElOQ0xVRElORyBORUdMSUdFTkNFIE9SIE9USEVSV0lT RSkgQVJJU0lORyBJTiBBTlkgV0FZIE9VVCBPRiBUSEUNCj4gPiArVVNFIE9GIFRISVMNCj4gPiAr ICogU09GVFdBUkUsIEVWRU4gSUYgQURWSVNFRCBPRiBUSEUgUE9TU0lCSUxJVFkgT0YgU1VDSCBE QU1BR0UuDQo+ID4gKyAqLw0KPiA+ICsNCj4gPiArL2luY2x1ZGUvICJmc2wvcDEwMjFzaS1wcmUu ZHRzaSINCj4gPiArLyB7DQo+ID4gKwltb2RlbCA9ICJmc2wsUDEwMjUiOw0KPiA+ICsJY29tcGF0 aWJsZSA9ICJmc2wsVFdSLVAxMDI1IjsNCj4gPiArDQo+ID4gKwltZW1vcnkgew0KPiA+ICsJCWRl dmljZV90eXBlID0gIm1lbW9yeSI7DQo+ID4gKwl9Ow0KPiA+ICsNCj4gPiArCWxiYzogbG9jYWxi dXNAZmZlMDUwMDAgew0KPiA+ICsJCXJlZyA9IDwwIDB4ZmZlMDUwMDAgMCAweDEwMDA+Ow0KPiA+ ICsNCj4gPiArCQkvKiBOT1IgRmxhc2ggYW5kIFNTRDEyODkgKi8NCj4gPiArCQlyYW5nZXMgPSA8 MHgwIDB4MCAweDAgMHhlYzAwMDAwMCAweDA0MDAwMDAwDQo+ID4gKwkJCSAgMHgyIDB4MCAweDAg MHhlMDAwMDAwMCAweDAwMDIwMDAwPjsNCj4gPiArCX07DQo+ID4gKw0KPiA+ICsJc29jOiBzb2NA ZmZlMDAwMDAgew0KPiA+ICsJCXJhbmdlcyA9IDwweDAgMHgwIDB4ZmZlMDAwMDAgMHgxMDAwMDA+ Ow0KPiA+ICsJfTsNCj4gPiArDQo+ID4gKwlwY2kwOiBwY2llQGZmZTA5MDAwIHsNCj4gPiArCQly YW5nZXMgPSA8MHgyMDAwMDAwIDB4MCAweGEwMDAwMDAwIDAgMHhhMDAwMDAwMCAweDANCj4gMHgy MDAwMDAwMA0KPiA+ICsJCQkgIDB4MTAwMDAwMCAweDAgMHgwMDAwMDAwMCAwIDB4ZmZjMTAwMDAg MHgwIDB4MTAwMDA+Ow0KPiA+ICsJCXJlZyA9IDwwIDB4ZmZlMDkwMDAgMCAweDEwMDA+Ow0KPiA+ ICsJCXBjaWVAMCB7DQo+ID4gKwkJCXJhbmdlcyA9IDwweDIwMDAwMDAgMHgwIDB4YTAwMDAwMDAN Cj4gPiArCQkJCSAgMHgyMDAwMDAwIDB4MCAweGEwMDAwMDAwDQo+ID4gKwkJCQkgIDB4MCAweDIw MDAwMDAwDQo+ID4gKw0KPiA+ICsJCQkJICAweDEwMDAwMDAgMHgwIDB4MA0KPiA+ICsJCQkJICAw eDEwMDAwMDAgMHgwIDB4MA0KPiA+ICsJCQkJICAweDAgMHgxMDAwMDA+Ow0KPiA+ICsJCX07DQo+ ID4gKwl9Ow0KPiA+ICsNCj4gPiArCXBjaTE6IHBjaWVAZmZlMGEwMDAgew0KPiA+ICsJCXJlZyA9 IDwwIDB4ZmZlMGEwMDAgMCAweDEwMDA+Ow0KPiA+ICsJCXJhbmdlcyA9IDwweDIwMDAwMDAgMHgw IDB4ODAwMDAwMDAgMCAweDgwMDAwMDAwIDB4MA0KPiAweDIwMDAwMDAwDQo+ID4gKwkJCSAgMHgx MDAwMDAwIDB4MCAweDAwMDAwMDAwIDAgMHhmZmMwMDAwMCAweDAgMHgxMDAwMD47DQo+ID4gKwkJ cGNpZUAwIHsNCj4gPiArCQkJcmFuZ2VzID0gPDB4MjAwMDAwMCAweDAgMHg4MDAwMDAwMA0KPiA+ ICsJCQkJICAweDIwMDAwMDAgMHgwIDB4ODAwMDAwMDANCj4gPiArCQkJCSAgMHgwIDB4MjAwMDAw MDANCj4gPiArDQo+ID4gKwkJCQkgIDB4MTAwMDAwMCAweDAgMHgwDQo+ID4gKwkJCQkgIDB4MTAw MDAwMCAweDAgMHgwDQo+ID4gKwkJCQkgIDB4MCAweDEwMDAwMD47DQo+ID4gKwkJfTsNCj4gPiAr CX07DQo+ID4gKw0KPiA+ICsJcWU6IHFlQGZmZTgwMDAwIHsNCj4gPiArCQlyYW5nZXMgPSA8MHgw IDB4MCAweGZmZTgwMDAwIDB4NDAwMDA+Ow0KPiA+ICsJCXJlZyA9IDwwIDB4ZmZlODAwMDAgMCAw eDQ4MD47DQo+ID4gKwkJYnJnLWZyZXF1ZW5jeSA9IDwwPjsNCj4gPiArCQlidXMtZnJlcXVlbmN5 ID0gPDA+Ow0KPiA+ICsJCXN0YXR1cyA9ICJkaXNhYmxlZCI7IC8qIG5vIGZpcm13YXJlIGxvYWRl ZCAqLw0KPiA+ICsNCj4gPiArCQllbmV0MzogdWNjQDIwMDAgew0KPiA+ICsJCQlkZXZpY2VfdHlw ZSA9ICJuZXR3b3JrIjsNCj4gPiArCQkJY29tcGF0aWJsZSA9ICJ1Y2NfZ2V0aCI7DQo+ID4gKwkJ CXJ4LWNsb2NrLW5hbWUgPSAiY2xrMTIiOw0KPiA+ICsJCQl0eC1jbG9jay1uYW1lID0gImNsazki Ow0KPiA+ICsJCQlwaW8taGFuZGxlID0gPCZwaW8xPjsNCj4gPiArCQkJcGh5LWhhbmRsZSA9IDwm cWVfcGh5MD47DQo+ID4gKwkJCXBoeS1jb25uZWN0aW9uLXR5cGUgPSAibWlpIjsNCj4gPiArCQl9 Ow0KPiA+ICsNCj4gPiArCQltZGlvQDIxMjAgew0KPiA+ICsJCQlxZV9waHkwOiBldGhlcm5ldC1w aHlAMTggew0KPiA+ICsJCQkJaW50ZXJydXB0LXBhcmVudCA9IDwmbXBpYz47DQo+ID4gKwkJCQlp bnRlcnJ1cHRzID0gPDQgMSAwIDA+Ow0KPiA+ICsJCQkJcmVnID0gPDB4MTg+Ow0KPiA+ICsJCQkJ ZGV2aWNlX3R5cGUgPSAiZXRoZXJuZXQtcGh5IjsNCj4gPiArCQkJfTsNCj4gPiArCQkJcWVfcGh5 MTogZXRoZXJuZXQtcGh5QDE5IHsNCj4gPiArCQkJCWludGVycnVwdC1wYXJlbnQgPSA8Jm1waWM+ Ow0KPiA+ICsJCQkJaW50ZXJydXB0cyA9IDw1IDEgMCAwPjsNCj4gPiArCQkJCXJlZyA9IDwweDE5 PjsNCj4gPiArCQkJCWRldmljZV90eXBlID0gImV0aGVybmV0LXBoeSI7DQo+ID4gKwkJCX07DQo+ ID4gKwkJCXRiaS1waHlAMTEgew0KPiA+ICsJCQkJcmVnID0gPDB4MTE+Ow0KPiA+ICsJCQkJZGV2 aWNlX3R5cGUgPSAidGJpLXBoeSI7DQo+ID4gKwkJCX07DQo+ID4gKwkJfTsNCj4gPiArDQo+ID4g KwkJZW5ldDQ6IHVjY0AyNDAwIHsNCj4gPiArCQkJZGV2aWNlX3R5cGUgPSAibmV0d29yayI7DQo+ ID4gKwkJCWNvbXBhdGlibGUgPSAidWNjX2dldGgiOw0KPiA+ICsJCQlyeC1jbG9jay1uYW1lID0g Im5vbmUiOw0KPiA+ICsJCQl0eC1jbG9jay1uYW1lID0gImNsazEzIjsNCj4gPiArCQkJcGlvLWhh bmRsZSA9IDwmcGlvMj47DQo+ID4gKwkJCXBoeS1oYW5kbGUgPSA8JnFlX3BoeTE+Ow0KPiA+ICsJ CQlwaHktY29ubmVjdGlvbi10eXBlID0gInJtaWkiOw0KPiA+ICsJCX07DQo+ID4gKwl9Ow0KPiA+ ICt9Ow0KPiANCj4gRG9uJ3QgZHVwbGljYXRlIGFsbCB0aGlzIGp1c3QgZm9yIDMyLzM2IGJpdC4g IFVzZSBhIGR0c2kgZm9yIChlLmcuKSB0aGUNCj4gY29udGVudHMgb2YgdGhlIFFFIG5vZGUuDQoN Ckkgd2lsbCByZW1vdmUgUUUgbm9kZSB0byBkdHNpIGZpbGUuDQoNCj4gDQo+IElzIHRoZXJlIGEg c3Ryb25nIG5lZWQgdG8gc3VwcG9ydCBib3RoIDMyIGFuZCAzNiBiaXQgaW4gdGhlIGZpcnN0IHBs YWNlPw0KDQpEb24ndCBoYXZlIHN0cm9uZyBuZWVkIHRvIHN1cHBvcnQgMzYgYml0IGZvciBUV1Iu IERvZXMgaXQgbWVhbiB0aGF0IEkgY2FuIG5hbWUgdGhlIGZpbGUgInAxMDI1dHdyLmR0cyIgaW5z dGVhZCBvZiAicDEwMjV0d3JfMzJiLmR0cyI/DQoNCj4gDQo+ID4gKy8qDQo+ID4gKyoqKioqKioq KioqKioqKioqKioqKioqKioqKioqKioqKioqKioqKioqKioqKioqKioqKioqKioqKioqKioqKioq KioqKg0KPiA+ICsqKioNCj4gPiArICoNCj4gPiArICogU2V0dXAgdGhlIGFyY2hpdGVjdHVyZQ0K PiA+ICsgKg0KPiA+ICsgKi8NCj4gPiArc3RhdGljIHZvaWQgX19pbml0IHR3cl9wMTAyNV9zZXR1 cF9hcmNoKHZvaWQpIHsgI2lmZGVmDQo+ID4gK0NPTkZJR19RVUlDQ19FTkdJTkUNCj4gPiArCXN0 cnVjdCBkZXZpY2Vfbm9kZSAqbnA7DQo+ID4gKyNlbmRpZg0KPiA+ICsNCj4gPiArCWlmIChwcGNf bWQucHJvZ3Jlc3MpDQo+ID4gKwkJcHBjX21kLnByb2dyZXNzKCJ0d3JfcDEwMjVfc2V0dXBfYXJj aCgpIiwgMCk7DQo+ID4gKw0KPiA+ICsJbXBjODV4eF9zbXBfaW5pdCgpOw0KPiA+ICsNCj4gPiAr CWZzbF9wY2lfYXNzaWduX3ByaW1hcnkoKTsNCj4gPiArDQo+ID4gKyNpZmRlZiBDT05GSUdfUVVJ Q0NfRU5HSU5FDQo+ID4gKwltcGM4NXh4X3FlX2luaXQoKTsNCj4gPiArDQo+ID4gKyNpZiBkZWZp bmVkKENPTkZJR19VQ0NfR0VUSCkgfHwgZGVmaW5lZChDT05GSUdfU0VSSUFMX1FFKQ0KPiA+ICsJ aWYgKG1hY2hpbmVfaXModHdyX3AxMDI1KSkgew0KPiA+ICsJCXN0cnVjdCBjY3NyX2d1dHMgX19p b21lbSAqZ3V0czsNCj4gPiArDQo+ID4gKwkJbnAgPSBvZl9maW5kX25vZGVfYnlfbmFtZShOVUxM LCAiZ2xvYmFsLXV0aWxpdGllcyIpOw0KPiANCj4gTG9vayBmb3IgaXQgYnkgY29tcGF0aWJsZS4N Cg0KT0suDQoNCj4gDQo+ID4gKwkJaWYgKG5wKSB7DQo+ID4gKwkJCWd1dHMgPSBvZl9pb21hcChu cCwgMCk7DQo+ID4gKwkJCWlmICghZ3V0cykNCj4gPiArCQkJCXByX2VycigidHdyX3AxMDI1OiBj b3VsZCBub3QgbWFwIg0KPiA+ICsJCQkJCSJnbG9iYWwgdXRpbGl0aWVzIHJlZ2lzdGVyXG4iKTsN Cj4gDQo+IERvbid0IGxpbmV3cmFwIHByaW50ZWQgc3RyaW5nIGNvbnN0YW50cyAodGhpcyBpcyBh biBleGNlcHRpb24gdG8gdGhlIDgwLQ0KPiBjb2x1bW4gcnVsZSkuDQoNCk9LLCBJIHdpbGwgZml4 IGl0Lg0KDQo+IA0KPiA+ICsJCQllbHNlIHsNCj4gPiArCQkJLyogUDEwMjUgaGFzIHBpbnMgbXV4 ZWQgZm9yIFFFIGFuZCBvdGhlciBmdW5jdGlvbnMuIFRvDQo+ID4gKwkJCSAqIGVuYWJsZSBRRSBV RUMgbW9kZSwgd2UgbmVlZCB0byBzZXQgYml0IFFFMCBmb3IgVUNDMQ0KPiA+ICsJCQkgKiBpbiBF dGggbW9kZSwgUUUwIGFuZCBRRTMgZm9yIFVDQzUgaW4gRXRoIG1vZGUsIFFFOQ0KPiA+ICsJCQkg KiBhbmQgUUUxMiBmb3IgUUUgTUlJIG1hbmFnZW1lbnQgc2lnbmFscyBpbiBQTVVYQ1INCj4gPiAr CQkJICogcmVnaXN0ZXIuDQo+ID4gKwkJCSAqLw0KPiA+ICsNCj4gPiArCQkJcHJpbnRrKEtFUk5f SU5GTyAiUDEwMjUgcGlubXV4IGNvbmZpZ3VyZWQgZm9yIFFFXG4iKTsNCj4gDQo+IEJhZCBpbmRl bnRhdGlvbiwgYW5kIHVzZSBwcl9pbmZvKCkgKG9yIGJldHRlciwganVzdCByZW1vdmUgaXQ7IGl0 J3MNCj4gaW1wbGllZCBieSB0aGUgYWJzZW5jZSBvZiB0aGUgZXJyb3Igb24gdGhlIG90aGVyIGJy YW5jaCBvZiB0aGUgaWYpLg0KDQpPaywgSSB3aWxsIHJlbW92ZSBpdC4NCg0KPiANCj4gPiArDQo+ ID4gKwkJCS8qIFNldCBRRSBtdXggYml0cyBpbiBQTVVYQ1IgKi8NCj4gPiArCQkJc2V0Yml0czMy KCZndXRzLT5wbXV4Y3IsIE1QQzg1eHhfUE1VWENSX1FFKDApIHwNCj4gPiArCQkJCQlNUEM4NXh4 X1BNVVhDUl9RRSgzKSB8DQo+ID4gKwkJCQkJTVBDODV4eF9QTVVYQ1JfUUUoOSkgfA0KPiA+ICsJ CQkJCU1QQzg1eHhfUE1VWENSX1FFKDEyKSk7DQo+ID4gKwkJCWlvdW5tYXAoZ3V0cyk7DQo+ID4g Kw0KPiA+ICsjaWYgZGVmaW5lZChDT05GSUdfU0VSSUFMX1FFKQ0KPiA+ICsJCQkvKiBPbiBQMTAy NVRXUiBib2FyZCwgdGhlIFVDQzcgYWN0ZWQgYXMgVUFSVCBwb3J0Lg0KPiA+ICsJCQkgKiBIb3dl dmVyLCBUaGUgVUNDNydzIENUUyBwaW4gaXMgbG93IGxldmVsIGluIGRlZmF1bHQsDQo+ID4gKwkJ CSAqIGl0IHdpbGwgaW1wYWN0IHRoZSB0cmFuc21pc3Npb24gaW4gZnVsbCBkdXBsZXgNCj4gPiAr CQkJICogY29tbXVuaWNhdGlvbi4gU28gZGlzYWJsZSB0aGUgRmxvdyBjb250cm9sIHBpbiBQQTE4 Lg0KPiA+ICsJCQkgKiBUaGUgVUNDNyBVQVJUIGp1c3QgY2FuIHVzZSBSWEQgYW5kIFRYRCBwaW5z Lg0KPiA+ICsJCQkgKi8NCj4gPiArCQkJcGFyX2lvX2NvbmZpZ19waW4oMCwgMTgsIDAsIDAsIDAs IDApOyAjZW5kaWYNCj4gDQo+IEFueSByZWFzb24gbm90IHRvIGRvIHRoaXMgdW5jb25kaXRpb25h bGx5Pw0KDQpUaGlzIGlzIGEgYm9hcmQgaXNzdWUsIHRoZSBjb2RlIGFscmVhZHkgaGF2ZSBhIGNv bmRpdGlvbiAtIGRlZmluZWQgU0VSSUFMX1FFLCBhbmQgSSB3aWxsIGFkZCBhIGNvbmRpdGlvbiAi aWYgKG1hY2hpbmVfaXModHdyX3AxMDI1KSkiLg0KDQo+IA0KPiAtU2NvdHQNCj4gDQoNCg== ^ permalink raw reply [flat|nested] 14+ messages in thread
* Re: [PATCH V4 3/3] powerpc/85xx: Add TWR-P1025 board support 2013-09-25 9:50 ` Xie Xiaobo-R63061 @ 2013-09-25 23:09 ` Scott Wood 2013-09-26 9:27 ` Xie Xiaobo-R63061 2013-09-27 17:03 ` Scott Wood 1 sibling, 1 reply; 14+ messages in thread From: Scott Wood @ 2013-09-25 23:09 UTC (permalink / raw) To: Xie Xiaobo-R63061 Cc: Wood Scott-B07421, linuxppc-dev@lists.ozlabs.org, Johnston Michael-R49610 On Wed, 2013-09-25 at 04:50 -0500, Xie Xiaobo-R63061 wrote: > Hi Scott, > > See the reply inline. > > > -----Original Message----- > > From: Wood Scott-B07421 > > Sent: Wednesday, September 25, 2013 7:22 AM > > To: Xie Xiaobo-R63061 > > Cc: linuxppc-dev@lists.ozlabs.org; Johnston Michael-R49610 > > Subject: Re: [PATCH V4 3/3] powerpc/85xx: Add TWR-P1025 board support > > > > On Tue, 2013-09-24 at 18:48 +0800, Xie Xiaobo wrote: > > > + partition@80000 { > > > + /* 3.5 MB for Linux Kernel Image */ > > > + reg = <0x00080000 0x00380000>; > > > + label = "NOR Linux Kernel Image"; > > > + }; > > > > Is this enough? > > I will enlarge it to 6MB. > > > > > > + partition@400000 { > > > + /* 58.75MB for JFFS2 based Root file System */ > > > + reg = <0x00400000 0x03ac0000>; > > > + label = "NOR Root File System"; > > > + }; > > > > Don't specify jffs2. > > OK, I will remove "jffs2" > > > > > > + /* CS2 for Display */ > > > + ssd1289@2,0 { > > > + #address-cells = <1>; > > > + #size-cells = <1>; > > > + compatible = "ssd1289"; > > > + reg = <0x2 0x0000 0x0002 > > > + 0x2 0x0002 0x0002>; > > > + }; > > > > Node names should be generic. What does ssd1289 do? If this is actually > > the display device, then it should be called "display@2,0". > > OK. The ssd1289 is a LCD controller. > > > > > How about a vendor prefix on that compatible? Why #address-cells/#size- > > cells despite no child nodes? Where is a binding that says what each of > > those two reg resources mean? > > I will add the vendor prefix. I review the ssd1289 driver, and the #address-cells/#size-cells were un-used. I will remove them. And a binding? Why do you need two separate reg resources rather than just <2 0 4>? Will they ever be discontiguous? -Scott ^ permalink raw reply [flat|nested] 14+ messages in thread
* RE: [PATCH V4 3/3] powerpc/85xx: Add TWR-P1025 board support 2013-09-25 23:09 ` Scott Wood @ 2013-09-26 9:27 ` Xie Xiaobo-R63061 2013-09-26 21:27 ` Scott Wood 0 siblings, 1 reply; 14+ messages in thread From: Xie Xiaobo-R63061 @ 2013-09-26 9:27 UTC (permalink / raw) To: Wood Scott-B07421; +Cc: Johnston Michael-R49610, linuxppc-dev@lists.ozlabs.org PiAtLS0tLU9yaWdpbmFsIE1lc3NhZ2UtLS0tLQ0KPiBGcm9tOiBXb29kIFNjb3R0LUIwNzQyMQ0K PiBTZW50OiBUaHVyc2RheSwgU2VwdGVtYmVyIDI2LCAyMDEzIDc6MTAgQU0NCj4gVG86IFhpZSBY aWFvYm8tUjYzMDYxDQo+IENjOiBXb29kIFNjb3R0LUIwNzQyMTsgbGludXhwcGMtZGV2QGxpc3Rz Lm96bGFicy5vcmc7IEpvaG5zdG9uIE1pY2hhZWwtDQo+IFI0OTYxMA0KPiBTdWJqZWN0OiBSZTog W1BBVENIIFY0IDMvM10gcG93ZXJwYy84NXh4OiBBZGQgVFdSLVAxMDI1IGJvYXJkIHN1cHBvcnQN Cj4gDQo+IE9uIFdlZCwgMjAxMy0wOS0yNSBhdCAwNDo1MCAtMDUwMCwgWGllIFhpYW9iby1SNjMw NjEgd3JvdGU6DQo+ID4gSGkgU2NvdHQsDQo+ID4NCj4gPiBTZWUgdGhlIHJlcGx5IGlubGluZS4N Cj4gPg0KPiA+ID4gLS0tLS1PcmlnaW5hbCBNZXNzYWdlLS0tLS0NCj4gPiA+IEZyb206IFdvb2Qg U2NvdHQtQjA3NDIxDQo+ID4gPiBTZW50OiBXZWRuZXNkYXksIFNlcHRlbWJlciAyNSwgMjAxMyA3 OjIyIEFNDQo+ID4gPiBUbzogWGllIFhpYW9iby1SNjMwNjENCj4gPiA+IENjOiBsaW51eHBwYy1k ZXZAbGlzdHMub3psYWJzLm9yZzsgSm9obnN0b24gTWljaGFlbC1SNDk2MTANCj4gPiA+IFN1Ympl Y3Q6IFJlOiBbUEFUQ0ggVjQgMy8zXSBwb3dlcnBjLzg1eHg6IEFkZCBUV1ItUDEwMjUgYm9hcmQN Cj4gPiA+IHN1cHBvcnQNCj4gPiA+DQo+ID4gPiBPbiBUdWUsIDIwMTMtMDktMjQgYXQgMTg6NDgg KzA4MDAsIFhpZSBYaWFvYm8gd3JvdGU6DQo+ID4gPiA+ICsJCXBhcnRpdGlvbkA4MDAwMCB7DQo+ ID4gPiA+ICsJCQkvKiAzLjUgTUIgZm9yIExpbnV4IEtlcm5lbCBJbWFnZSAqLw0KPiA+ID4gPiAr CQkJcmVnID0gPDB4MDAwODAwMDAgMHgwMDM4MDAwMD47DQo+ID4gPiA+ICsJCQlsYWJlbCA9ICJO T1IgTGludXggS2VybmVsIEltYWdlIjsNCj4gPiA+ID4gKwkJfTsNCj4gPiA+DQo+ID4gPiBJcyB0 aGlzIGVub3VnaD8NCj4gPg0KPiA+IEkgd2lsbCBlbmxhcmdlIGl0IHRvIDZNQi4NCj4gPg0KPiA+ ID4NCj4gPiA+ID4gKwkJcGFydGl0aW9uQDQwMDAwMCB7DQo+ID4gPiA+ICsJCQkvKiA1OC43NU1C IGZvciBKRkZTMiBiYXNlZCBSb290IGZpbGUgU3lzdGVtICovDQo+ID4gPiA+ICsJCQlyZWcgPSA8 MHgwMDQwMDAwMCAweDAzYWMwMDAwPjsNCj4gPiA+ID4gKwkJCWxhYmVsID0gIk5PUiBSb290IEZp bGUgU3lzdGVtIjsNCj4gPiA+ID4gKwkJfTsNCj4gPiA+DQo+ID4gPiBEb24ndCBzcGVjaWZ5IGpm ZnMyLg0KPiA+DQo+ID4gT0ssIEkgd2lsbCByZW1vdmUgImpmZnMyIg0KPiA+DQo+ID4gPg0KPiA+ ID4gPiArCS8qIENTMiBmb3IgRGlzcGxheSAqLw0KPiA+ID4gPiArCXNzZDEyODlAMiwwIHsNCj4g PiA+ID4gKwkJI2FkZHJlc3MtY2VsbHMgPSA8MT47DQo+ID4gPiA+ICsJCSNzaXplLWNlbGxzID0g PDE+Ow0KPiA+ID4gPiArCQljb21wYXRpYmxlID0gInNzZDEyODkiOw0KPiA+ID4gPiArCQlyZWcg PSA8MHgyIDB4MDAwMCAweDAwMDINCj4gPiA+ID4gKwkJICAgICAgIDB4MiAweDAwMDIgMHgwMDAy PjsNCj4gPiA+ID4gKwl9Ow0KPiA+ID4NCj4gPiA+IE5vZGUgbmFtZXMgc2hvdWxkIGJlIGdlbmVy aWMuICBXaGF0IGRvZXMgc3NkMTI4OSBkbz8gIElmIHRoaXMgaXMNCj4gPiA+IGFjdHVhbGx5IHRo ZSBkaXNwbGF5IGRldmljZSwgdGhlbiBpdCBzaG91bGQgYmUgY2FsbGVkICJkaXNwbGF5QDIsMCIu DQo+ID4NCj4gPiBPSy4gVGhlIHNzZDEyODkgaXMgYSBMQ0QgY29udHJvbGxlci4NCj4gPg0KPiA+ ID4NCj4gPiA+IEhvdyBhYm91dCBhIHZlbmRvciBwcmVmaXggb24gdGhhdCBjb21wYXRpYmxlPyAg V2h5DQo+ID4gPiAjYWRkcmVzcy1jZWxscy8jc2l6ZS0gY2VsbHMgZGVzcGl0ZSBubyBjaGlsZCBu b2Rlcz8gIFdoZXJlIGlzIGENCj4gPiA+IGJpbmRpbmcgdGhhdCBzYXlzIHdoYXQgZWFjaCBvZiB0 aG9zZSB0d28gcmVnIHJlc291cmNlcyBtZWFuPw0KPiA+DQo+ID4gSSB3aWxsIGFkZCB0aGUgdmVu ZG9yIHByZWZpeC4gSSByZXZpZXcgdGhlIHNzZDEyODkgZHJpdmVyLCBhbmQgdGhlDQo+ICNhZGRy ZXNzLWNlbGxzLyNzaXplLWNlbGxzIHdlcmUgdW4tdXNlZC4gSSB3aWxsIHJlbW92ZSB0aGVtLg0K PiANCj4gQW5kIGEgYmluZGluZz8NCj4gDQo+IFdoeSBkbyB5b3UgbmVlZCB0d28gc2VwYXJhdGUg cmVnIHJlc291cmNlcyByYXRoZXIgdGhhbiBqdXN0IDwyIDAgND4/DQo+IFdpbGwgdGhleSBldmVy IGJlIGRpc2NvbnRpZ3VvdXM/DQoNCltYaWVdIEkgcmV2aWV3IHRoZSBzc2QxMjg5IGRyaXZlciBj b2RlLCBhbmQgZm91bmQgdGhlIGRyaXZlciBuZWVkIHR3byByZWcgcmVzb3VyY2VzLCBpZiBjaGFu Z2UgdGhlIGR0cywgdGhlIGRyaXZlciBhbHNvIHNob3VsZCBiZSBtb2RpZmllZCBhY2NvcmRpbmds eS4gU28gSSByZW1vdmUgdGhlIHNzZDEyODkgbm9kZSBmcm9tIHRoaXMgcGF0Y2guIEkgd2lsbCBz dWJtaXQgbmV3IHBhdGNoIGluY2x1ZGUgdGhlIGR0cyBtb2RpZmljYXRpb24sIHNzZDEyODkgZHJp dmVyIGFuZCB0aGUgYmluZGluZy4gICANCg0KPiANCj4gLVNjb3R0DQo+IA0KDQo= ^ permalink raw reply [flat|nested] 14+ messages in thread
* Re: [PATCH V4 3/3] powerpc/85xx: Add TWR-P1025 board support 2013-09-26 9:27 ` Xie Xiaobo-R63061 @ 2013-09-26 21:27 ` Scott Wood 2013-11-06 2:31 ` Xiaobo Xie 0 siblings, 1 reply; 14+ messages in thread From: Scott Wood @ 2013-09-26 21:27 UTC (permalink / raw) To: Xie Xiaobo-R63061 Cc: Wood Scott-B07421, linuxppc-dev@lists.ozlabs.org, Johnston Michael-R49610 On Thu, 2013-09-26 at 04:27 -0500, Xie Xiaobo-R63061 wrote: > > -----Original Message----- > > From: Wood Scott-B07421 > > Sent: Thursday, September 26, 2013 7:10 AM > > To: Xie Xiaobo-R63061 > > Cc: Wood Scott-B07421; linuxppc-dev@lists.ozlabs.org; Johnston Michael- > > R49610 > > Subject: Re: [PATCH V4 3/3] powerpc/85xx: Add TWR-P1025 board support > > > > On Wed, 2013-09-25 at 04:50 -0500, Xie Xiaobo-R63061 wrote: > > > Hi Scott, > > > > > > See the reply inline. > > > > > > > -----Original Message----- > > > > From: Wood Scott-B07421 > > > > Sent: Wednesday, September 25, 2013 7:22 AM > > > > To: Xie Xiaobo-R63061 > > > > Cc: linuxppc-dev@lists.ozlabs.org; Johnston Michael-R49610 > > > > Subject: Re: [PATCH V4 3/3] powerpc/85xx: Add TWR-P1025 board > > > > support > > > > > > > > On Tue, 2013-09-24 at 18:48 +0800, Xie Xiaobo wrote: > > > > > + partition@80000 { > > > > > + /* 3.5 MB for Linux Kernel Image */ > > > > > + reg = <0x00080000 0x00380000>; > > > > > + label = "NOR Linux Kernel Image"; > > > > > + }; > > > > > > > > Is this enough? > > > > > > I will enlarge it to 6MB. > > > > > > > > > > > > + partition@400000 { > > > > > + /* 58.75MB for JFFS2 based Root file System */ > > > > > + reg = <0x00400000 0x03ac0000>; > > > > > + label = "NOR Root File System"; > > > > > + }; > > > > > > > > Don't specify jffs2. > > > > > > OK, I will remove "jffs2" > > > > > > > > > > > > + /* CS2 for Display */ > > > > > + ssd1289@2,0 { > > > > > + #address-cells = <1>; > > > > > + #size-cells = <1>; > > > > > + compatible = "ssd1289"; > > > > > + reg = <0x2 0x0000 0x0002 > > > > > + 0x2 0x0002 0x0002>; > > > > > + }; > > > > > > > > Node names should be generic. What does ssd1289 do? If this is > > > > actually the display device, then it should be called "display@2,0". > > > > > > OK. The ssd1289 is a LCD controller. > > > > > > > > > > > How about a vendor prefix on that compatible? Why > > > > #address-cells/#size- cells despite no child nodes? Where is a > > > > binding that says what each of those two reg resources mean? > > > > > > I will add the vendor prefix. I review the ssd1289 driver, and the > > #address-cells/#size-cells were un-used. I will remove them. > > > > And a binding? > > > > Why do you need two separate reg resources rather than just <2 0 4>? > > Will they ever be discontiguous? > > [Xie] I review the ssd1289 driver code, and found the driver need two reg resources, The device tree describes the hardware, not the current state of Linux drivers. Especially drivers that aren't yet in Linux. :-) > if change the dts, the driver also should be modified accordingly. So I > remove the ssd1289 node from this patch. I will submit new patch > include the dts modification, ssd1289 driver and the binding. Ideally all devices (and bindings) should be described when the device tree is initally added, regardless of whether you have a driver yet. -Scott ^ permalink raw reply [flat|nested] 14+ messages in thread
* RE: [PATCH V4 3/3] powerpc/85xx: Add TWR-P1025 board support 2013-09-26 21:27 ` Scott Wood @ 2013-11-06 2:31 ` Xiaobo Xie 0 siblings, 0 replies; 14+ messages in thread From: Xiaobo Xie @ 2013-11-06 2:31 UTC (permalink / raw) To: Scott Wood; +Cc: Michael Johnston, linuxppc-dev@lists.ozlabs.org SGkgU2NvdHQsDQoNCj4gLS0tLS1PcmlnaW5hbCBNZXNzYWdlLS0tLS0NCj4gRnJvbTogV29vZCBT Y290dC1CMDc0MjENCj4gU2VudDogRnJpZGF5LCBTZXB0ZW1iZXIgMjcsIDIwMTMgNToyNyBBTQ0K PiBUbzogWGllIFhpYW9iby1SNjMwNjENCj4gQ2M6IFdvb2QgU2NvdHQtQjA3NDIxOyBsaW51eHBw Yy1kZXZAbGlzdHMub3psYWJzLm9yZzsgSm9obnN0b24gTWljaGFlbC0NCj4gUjQ5NjEwDQo+IFN1 YmplY3Q6IFJlOiBbUEFUQ0ggVjQgMy8zXSBwb3dlcnBjLzg1eHg6IEFkZCBUV1ItUDEwMjUgYm9h cmQgc3VwcG9ydA0KPiANCj4gPiA+ID4gPiA+ICsJLyogQ1MyIGZvciBEaXNwbGF5ICovDQo+ID4g PiA+ID4gPiArCXNzZDEyODlAMiwwIHsNCj4gPiA+ID4gPiA+ICsJCSNhZGRyZXNzLWNlbGxzID0g PDE+Ow0KPiA+ID4gPiA+ID4gKwkJI3NpemUtY2VsbHMgPSA8MT47DQo+ID4gPiA+ID4gPiArCQlj b21wYXRpYmxlID0gInNzZDEyODkiOw0KPiA+ID4gPiA+ID4gKwkJcmVnID0gPDB4MiAweDAwMDAg MHgwMDAyDQo+ID4gPiA+ID4gPiArCQkgICAgICAgMHgyIDB4MDAwMiAweDAwMDI+Ow0KPiA+ID4g PiA+ID4gKwl9Ow0KPiA+ID4gPiA+DQo+ID4gPiA+ID4gTm9kZSBuYW1lcyBzaG91bGQgYmUgZ2Vu ZXJpYy4gIFdoYXQgZG9lcyBzc2QxMjg5IGRvPyAgSWYgdGhpcyBpcw0KPiA+ID4gPiA+IGFjdHVh bGx5IHRoZSBkaXNwbGF5IGRldmljZSwgdGhlbiBpdCBzaG91bGQgYmUgY2FsbGVkDQo+ICJkaXNw bGF5QDIsMCIuDQo+ID4gPiA+DQo+ID4gPiA+IE9LLiBUaGUgc3NkMTI4OSBpcyBhIExDRCBjb250 cm9sbGVyLg0KPiA+ID4gPg0KPiA+ID4gPiA+DQo+ID4gPiA+ID4gSG93IGFib3V0IGEgdmVuZG9y IHByZWZpeCBvbiB0aGF0IGNvbXBhdGlibGU/ICBXaHkNCj4gPiA+ID4gPiAjYWRkcmVzcy1jZWxs cy8jc2l6ZS0gY2VsbHMgZGVzcGl0ZSBubyBjaGlsZCBub2Rlcz8gIFdoZXJlIGlzIGENCj4gPiA+ ID4gPiBiaW5kaW5nIHRoYXQgc2F5cyB3aGF0IGVhY2ggb2YgdGhvc2UgdHdvIHJlZyByZXNvdXJj ZXMgbWVhbj8NCj4gPiA+ID4NCj4gPiA+ID4gSSB3aWxsIGFkZCB0aGUgdmVuZG9yIHByZWZpeC4g SSByZXZpZXcgdGhlIHNzZDEyODkgZHJpdmVyLCBhbmQgdGhlDQo+ID4gPiAjYWRkcmVzcy1jZWxs cy8jc2l6ZS1jZWxscyB3ZXJlIHVuLXVzZWQuIEkgd2lsbCByZW1vdmUgdGhlbS4NCj4gPiA+DQo+ ID4gPiBBbmQgYSBiaW5kaW5nPw0KPiA+ID4NCj4gPiA+IFdoeSBkbyB5b3UgbmVlZCB0d28gc2Vw YXJhdGUgcmVnIHJlc291cmNlcyByYXRoZXIgdGhhbiBqdXN0IDwyIDAgND4/DQo+ID4gPiBXaWxs IHRoZXkgZXZlciBiZSBkaXNjb250aWd1b3VzPw0KPiA+DQo+ID4gW1hpZV0gSSByZXZpZXcgdGhl IHNzZDEyODkgZHJpdmVyIGNvZGUsIGFuZCBmb3VuZCB0aGUgZHJpdmVyIG5lZWQgdHdvDQo+ID4g cmVnIHJlc291cmNlcywNCj4gDQo+IFRoZSBkZXZpY2UgdHJlZSBkZXNjcmliZXMgdGhlIGhhcmR3 YXJlLCBub3QgdGhlIGN1cnJlbnQgc3RhdGUgb2YgTGludXgNCj4gZHJpdmVycy4gIEVzcGVjaWFs bHkgZHJpdmVycyB0aGF0IGFyZW4ndCB5ZXQgaW4gTGludXguIDotKQ0KPiANCg0KT0ssIEkgd2ls bCByZW1haW4gdGhlIGRpc3BsYXkgbm9kZS4NCg0KPiA+IGlmIGNoYW5nZSB0aGUgZHRzLCB0aGUg ZHJpdmVyIGFsc28gc2hvdWxkIGJlIG1vZGlmaWVkIGFjY29yZGluZ2x5LiBTbw0KPiA+IEkgcmVt b3ZlIHRoZSBzc2QxMjg5IG5vZGUgZnJvbSB0aGlzIHBhdGNoLiBJIHdpbGwgc3VibWl0IG5ldyBw YXRjaA0KPiA+IGluY2x1ZGUgdGhlIGR0cyBtb2RpZmljYXRpb24sIHNzZDEyODkgZHJpdmVyIGFu ZCB0aGUgYmluZGluZy4NCj4gDQo+IElkZWFsbHkgYWxsIGRldmljZXMgKGFuZCBiaW5kaW5ncykg c2hvdWxkIGJlIGRlc2NyaWJlZCB3aGVuIHRoZSBkZXZpY2UNCj4gdHJlZSBpcyBpbml0YWxseSBh ZGRlZCwgcmVnYXJkbGVzcyBvZiB3aGV0aGVyIHlvdSBoYXZlIGEgZHJpdmVyIHlldC4NCj4gDQog DQpJIHdpbGwgYWRkIGEgYmluZGluZyBkb2N1bWVudCBmb3IgdGhlIHNzZDEyODkgZGV2aWNlLg0K DQo+IC1TY290dA0KPiANCi0gWGlhb2JvDQo= ^ permalink raw reply [flat|nested] 14+ messages in thread
* Re: [PATCH V4 3/3] powerpc/85xx: Add TWR-P1025 board support 2013-09-25 9:50 ` Xie Xiaobo-R63061 2013-09-25 23:09 ` Scott Wood @ 2013-09-27 17:03 ` Scott Wood 2013-10-25 9:49 ` Xie Xiaobo-R63061 1 sibling, 1 reply; 14+ messages in thread From: Scott Wood @ 2013-09-27 17:03 UTC (permalink / raw) To: Xie Xiaobo-R63061 Cc: Wood Scott-B07421, linuxppc-dev@lists.ozlabs.org, Johnston Michael-R49610 On Wed, 2013-09-25 at 04:50 -0500, Xie Xiaobo-R63061 wrote: > > > +#if defined(CONFIG_SERIAL_QE) > > > + /* On P1025TWR board, the UCC7 acted as UART port. > > > + * However, The UCC7's CTS pin is low level in default, > > > + * it will impact the transmission in full duplex > > > + * communication. So disable the Flow control pin PA18. > > > + * The UCC7 UART just can use RXD and TXD pins. > > > + */ > > > + par_io_config_pin(0, 18, 0, 0, 0, 0); #endif > > > > Any reason not to do this unconditionally? > > This is a board issue, the code already have a condition - defined > SERIAL_QE, and I will add a condition "if (machine_is(twr_p1025))". My point was, is there any harm in doing this without regard to CONFIG_SERIAL_QE? -Scott ^ permalink raw reply [flat|nested] 14+ messages in thread
* RE: [PATCH V4 3/3] powerpc/85xx: Add TWR-P1025 board support 2013-09-27 17:03 ` Scott Wood @ 2013-10-25 9:49 ` Xie Xiaobo-R63061 0 siblings, 0 replies; 14+ messages in thread From: Xie Xiaobo-R63061 @ 2013-10-25 9:49 UTC (permalink / raw) To: Wood Scott-B07421; +Cc: Johnston Michael-R49610, linuxppc-dev@lists.ozlabs.org SGkgU2NvdHQsDQoNCj4gLS0tLS1PcmlnaW5hbCBNZXNzYWdlLS0tLS0NCj4gRnJvbTogV29vZCBT Y290dC1CMDc0MjENCj4gU2VudDogU2F0dXJkYXksIFNlcHRlbWJlciAyOCwgMjAxMyAxOjA0IEFN DQo+IFRvOiBYaWUgWGlhb2JvLVI2MzA2MQ0KPiBDYzogV29vZCBTY290dC1CMDc0MjE7IGxpbnV4 cHBjLWRldkBsaXN0cy5vemxhYnMub3JnOyBKb2huc3RvbiBNaWNoYWVsLQ0KPiBSNDk2MTANCj4g U3ViamVjdDogUmU6IFtQQVRDSCBWNCAzLzNdIHBvd2VycGMvODV4eDogQWRkIFRXUi1QMTAyNSBi b2FyZCBzdXBwb3J0DQo+IA0KPiBPbiBXZWQsIDIwMTMtMDktMjUgYXQgMDQ6NTAgLTA1MDAsIFhp ZSBYaWFvYm8tUjYzMDYxIHdyb3RlOg0KPiA+ID4gPiArI2lmIGRlZmluZWQoQ09ORklHX1NFUklB TF9RRSkNCj4gPiA+ID4gKwkJCS8qIE9uIFAxMDI1VFdSIGJvYXJkLCB0aGUgVUNDNyBhY3RlZCBh cyBVQVJUIHBvcnQuDQo+ID4gPiA+ICsJCQkgKiBIb3dldmVyLCBUaGUgVUNDNydzIENUUyBwaW4g aXMgbG93IGxldmVsIGluDQo+IGRlZmF1bHQsDQo+ID4gPiA+ICsJCQkgKiBpdCB3aWxsIGltcGFj dCB0aGUgdHJhbnNtaXNzaW9uIGluIGZ1bGwgZHVwbGV4DQo+ID4gPiA+ICsJCQkgKiBjb21tdW5p Y2F0aW9uLiBTbyBkaXNhYmxlIHRoZSBGbG93IGNvbnRyb2wgcGluDQo+IFBBMTguDQo+ID4gPiA+ ICsJCQkgKiBUaGUgVUNDNyBVQVJUIGp1c3QgY2FuIHVzZSBSWEQgYW5kIFRYRCBwaW5zLg0KPiA+ ID4gPiArCQkJICovDQo+ID4gPiA+ICsJCQlwYXJfaW9fY29uZmlnX3BpbigwLCAxOCwgMCwgMCwg MCwgMCk7ICNlbmRpZg0KPiA+ID4NCj4gPiA+IEFueSByZWFzb24gbm90IHRvIGRvIHRoaXMgdW5j b25kaXRpb25hbGx5Pw0KPiA+DQo+ID4gVGhpcyBpcyBhIGJvYXJkIGlzc3VlLCB0aGUgY29kZSBh bHJlYWR5IGhhdmUgYSBjb25kaXRpb24gLSBkZWZpbmVkDQo+ID4gU0VSSUFMX1FFLCBhbmQgSSB3 aWxsIGFkZCBhIGNvbmRpdGlvbiAiaWYgKG1hY2hpbmVfaXModHdyX3AxMDI1KSkiLg0KPiANCj4g TXkgcG9pbnQgd2FzLCBpcyB0aGVyZSBhbnkgaGFybSBpbiBkb2luZyB0aGlzIHdpdGhvdXQgcmVn YXJkIHRvDQo+IENPTkZJR19TRVJJQUxfUUU/DQoNClRoZSBDVFMgcGluIHdpbGwgYmUgdGhlIHBp biBvZiBwcm9maWJ1cyBpZiBhZGQgYSBwcm9maWJ1cyBleHBhbnNpb24gYm9hcmQgaW4gVFdSIHN5 c3RlbS4gSWYgZGlzYWJsZSB0aGUgcGluIHVuY29uZGl0aW9uYWxseSwgaXQgd2lsbCBhZmZlY3Qg dGhlIGZ1bmN0aW9uIG9mIHByb2ZpYnVzLiAgDQoNCi1YaWUgWGlhb2JvDQo+IA0KPiAtU2NvdHQN Cj4gDQoNCg== ^ permalink raw reply [flat|nested] 14+ messages in thread
* Re: [PATCH V4 1/3] powerpc/85xx: Add QE common init functions 2013-09-24 10:48 [PATCH V4 1/3] powerpc/85xx: Add QE common init functions Xie Xiaobo 2013-09-24 10:48 ` [PATCH V4 2/3] powerpc/85xx: Use common init functions for QE Xie Xiaobo 2013-09-24 10:48 ` [PATCH V4 3/3] powerpc/85xx: Add TWR-P1025 board support Xie Xiaobo @ 2013-09-24 23:13 ` Scott Wood 2013-09-25 9:51 ` Xie Xiaobo-R63061 2 siblings, 1 reply; 14+ messages in thread From: Scott Wood @ 2013-09-24 23:13 UTC (permalink / raw) To: Xie Xiaobo; +Cc: linuxppc-dev On Tue, 2013-09-24 at 18:48 +0800, Xie Xiaobo wrote: > Define two QE init functions in common file, and avoid > the same codes being duplicated in board files. > > Signed-off-by: Xie Xiaobo <X.Xie@freescale.com> > --- > V4 -> V3: Nochange > > arch/powerpc/platforms/85xx/common.c | 51 +++++++++++++++++++++++++++++++++++ > arch/powerpc/platforms/85xx/mpc85xx.h | 8 ++++++ > 2 files changed, 59 insertions(+) > > diff --git a/arch/powerpc/platforms/85xx/common.c b/arch/powerpc/platforms/85xx/common.c > index d0861a0..08fff48 100644 > --- a/arch/powerpc/platforms/85xx/common.c > +++ b/arch/powerpc/platforms/85xx/common.c > @@ -7,6 +7,9 @@ > */ > #include <linux/of_platform.h> > > +#include <asm/machdep.h> > +#include <asm/qe.h> > +#include <asm/qe_ic.h> > #include <sysdev/cpm2_pic.h> > > #include "mpc85xx.h" > @@ -80,3 +83,51 @@ void __init mpc85xx_cpm2_pic_init(void) > irq_set_chained_handler(irq, cpm2_cascade); > } > #endif > + > +#ifdef CONFIG_QUICC_ENGINE > +void __init mpc85xx_qe_pic_init(void) > +{ > + struct device_node *np; > + > + np = of_find_compatible_node(NULL, NULL, "fsl,qe-ic"); > + if (np) { > + if (machine_is(mpc8568_mds) || machine_is(mpc8569_mds)) > + qe_ic_init(np, 0, qe_ic_cascade_muxed_mpic, NULL); > + else > + qe_ic_init(np, 0, qe_ic_cascade_low_mpic, > + qe_ic_cascade_high_mpic); > + of_node_put(np); > + } else > + pr_err("%s: Could not find qe-ic node\n", __func__); > +} Have the caller pass in a flag indicating the type of cascade. Or, perhaps this function isn't worth factoring out. Where is the check for p1021_mds? Where did 8568/9 MDS come from? I don't see those checks removed in patch 2. BTW, when you move code from one place to another, do it in one patch. Don't add it in one patch and then remove it in another. A more useful split would have been one patch handling qe_init and another handling qe_pic_init. -Scott ^ permalink raw reply [flat|nested] 14+ messages in thread
* RE: [PATCH V4 1/3] powerpc/85xx: Add QE common init functions 2013-09-24 23:13 ` [PATCH V4 1/3] powerpc/85xx: Add QE common init functions Scott Wood @ 2013-09-25 9:51 ` Xie Xiaobo-R63061 2013-09-25 18:01 ` Scott Wood 0 siblings, 1 reply; 14+ messages in thread From: Xie Xiaobo-R63061 @ 2013-09-25 9:51 UTC (permalink / raw) To: Wood Scott-B07421; +Cc: linuxppc-dev@lists.ozlabs.org PiAtLS0tLU9yaWdpbmFsIE1lc3NhZ2UtLS0tLQ0KPiBGcm9tOiBXb29kIFNjb3R0LUIwNzQyMQ0K PiBTZW50OiBXZWRuZXNkYXksIFNlcHRlbWJlciAyNSwgMjAxMyA3OjEzIEFNDQo+IFRvOiBYaWUg WGlhb2JvLVI2MzA2MQ0KPiBDYzogbGludXhwcGMtZGV2QGxpc3RzLm96bGFicy5vcmcNCj4gU3Vi amVjdDogUmU6IFtQQVRDSCBWNCAxLzNdIHBvd2VycGMvODV4eDogQWRkIFFFIGNvbW1vbiBpbml0 IGZ1bmN0aW9ucw0KPiANCj4gT24gVHVlLCAyMDEzLTA5LTI0IGF0IDE4OjQ4ICswODAwLCBYaWUg WGlhb2JvIHdyb3RlOg0KPiA+IERlZmluZSB0d28gUUUgaW5pdCBmdW5jdGlvbnMgaW4gY29tbW9u IGZpbGUsIGFuZCBhdm9pZCB0aGUgc2FtZSBjb2Rlcw0KPiA+IGJlaW5nIGR1cGxpY2F0ZWQgaW4g Ym9hcmQgZmlsZXMuDQo+ID4NCj4gPiBTaWduZWQtb2ZmLWJ5OiBYaWUgWGlhb2JvIDxYLlhpZUBm cmVlc2NhbGUuY29tPg0KPiA+IC0tLQ0KPiA+IFY0IC0+IFYzOiBOb2NoYW5nZQ0KPiA+DQo+ID4g IGFyY2gvcG93ZXJwYy9wbGF0Zm9ybXMvODV4eC9jb21tb24uYyAgfCA1MQ0KPiA+ICsrKysrKysr KysrKysrKysrKysrKysrKysrKysrKysrKysrDQo+ID4gIGFyY2gvcG93ZXJwYy9wbGF0Zm9ybXMv ODV4eC9tcGM4NXh4LmggfCAgOCArKysrKysNCj4gPiAgMiBmaWxlcyBjaGFuZ2VkLCA1OSBpbnNl cnRpb25zKCspDQo+ID4NCj4gPiBkaWZmIC0tZ2l0IGEvYXJjaC9wb3dlcnBjL3BsYXRmb3Jtcy84 NXh4L2NvbW1vbi5jDQo+ID4gYi9hcmNoL3Bvd2VycGMvcGxhdGZvcm1zLzg1eHgvY29tbW9uLmMN Cj4gPiBpbmRleCBkMDg2MWEwLi4wOGZmZjQ4IDEwMDY0NA0KPiA+IC0tLSBhL2FyY2gvcG93ZXJw Yy9wbGF0Zm9ybXMvODV4eC9jb21tb24uYw0KPiA+ICsrKyBiL2FyY2gvcG93ZXJwYy9wbGF0Zm9y bXMvODV4eC9jb21tb24uYw0KPiA+IEBAIC03LDYgKzcsOSBAQA0KPiA+ICAgKi8NCj4gPiAgI2lu Y2x1ZGUgPGxpbnV4L29mX3BsYXRmb3JtLmg+DQo+ID4NCj4gPiArI2luY2x1ZGUgPGFzbS9tYWNo ZGVwLmg+DQo+ID4gKyNpbmNsdWRlIDxhc20vcWUuaD4NCj4gPiArI2luY2x1ZGUgPGFzbS9xZV9p Yy5oPg0KPiA+ICAjaW5jbHVkZSA8c3lzZGV2L2NwbTJfcGljLmg+DQo+ID4NCj4gPiAgI2luY2x1 ZGUgIm1wYzg1eHguaCINCj4gPiBAQCAtODAsMyArODMsNTEgQEAgdm9pZCBfX2luaXQgbXBjODV4 eF9jcG0yX3BpY19pbml0KHZvaWQpDQo+ID4gIAlpcnFfc2V0X2NoYWluZWRfaGFuZGxlcihpcnEs IGNwbTJfY2FzY2FkZSk7ICB9ICAjZW5kaWYNCj4gPiArDQo+ID4gKyNpZmRlZiBDT05GSUdfUVVJ Q0NfRU5HSU5FDQo+ID4gK3ZvaWQgX19pbml0IG1wYzg1eHhfcWVfcGljX2luaXQodm9pZCkgew0K PiA+ICsJc3RydWN0IGRldmljZV9ub2RlICpucDsNCj4gPiArDQo+ID4gKwlucCA9IG9mX2ZpbmRf Y29tcGF0aWJsZV9ub2RlKE5VTEwsIE5VTEwsICJmc2wscWUtaWMiKTsNCj4gPiArCWlmIChucCkg ew0KPiA+ICsJCWlmIChtYWNoaW5lX2lzKG1wYzg1NjhfbWRzKSB8fCBtYWNoaW5lX2lzKG1wYzg1 NjlfbWRzKSkNCj4gPiArCQkJcWVfaWNfaW5pdChucCwgMCwgcWVfaWNfY2FzY2FkZV9tdXhlZF9t cGljLCBOVUxMKTsNCj4gPiArCQllbHNlDQo+ID4gKwkJCXFlX2ljX2luaXQobnAsIDAsIHFlX2lj X2Nhc2NhZGVfbG93X21waWMsDQo+ID4gKwkJCQkJcWVfaWNfY2FzY2FkZV9oaWdoX21waWMpOw0K PiA+ICsJCW9mX25vZGVfcHV0KG5wKTsNCj4gPiArCX0gZWxzZQ0KPiA+ICsJCXByX2VycigiJXM6 IENvdWxkIG5vdCBmaW5kIHFlLWljIG5vZGVcbiIsIF9fZnVuY19fKTsgfQ0KPiANCj4gSGF2ZSB0 aGUgY2FsbGVyIHBhc3MgaW4gYSBmbGFnIGluZGljYXRpbmcgdGhlIHR5cGUgb2YgY2FzY2FkZS4g IE9yLA0KPiBwZXJoYXBzIHRoaXMgZnVuY3Rpb24gaXNuJ3Qgd29ydGggZmFjdG9yaW5nIG91dC4g IFdoZXJlIGlzIHRoZSBjaGVjayBmb3INCj4gcDEwMjFfbWRzPyAgV2hlcmUgZGlkIDg1NjgvOSBN RFMgY29tZSBmcm9tPyAgSSBkb24ndCBzZWUgdGhvc2UgY2hlY2tzDQo+IHJlbW92ZWQgaW4gcGF0 Y2ggMi4NCg0KW1hpZV0gVGhlIHFlX3BpY19pbml0IGp1c3QgY2FsbCBvbmUgZnVuY3Rpb24gcWVf aWNfaW5pdCgpLCBTbyBJIGp1c3QgbmVlZCBmYWN0b3Igb3V0IHRoZSBxZV9pbml0IGZ1bmN0aW9u LCBJcyBpdCBmZWFzaWJsZT8NCiANCj4gDQo+IEJUVywgd2hlbiB5b3UgbW92ZSBjb2RlIGZyb20g b25lIHBsYWNlIHRvIGFub3RoZXIsIGRvIGl0IGluIG9uZSBwYXRjaC4NCj4gRG9uJ3QgYWRkIGl0 IGluIG9uZSBwYXRjaCBhbmQgdGhlbiByZW1vdmUgaXQgaW4gYW5vdGhlci4gIEEgbW9yZSB1c2Vm dWwNCj4gc3BsaXQgd291bGQgaGF2ZSBiZWVuIG9uZSBwYXRjaCBoYW5kbGluZyBxZV9pbml0IGFu ZCBhbm90aGVyIGhhbmRsaW5nDQo+IHFlX3BpY19pbml0Lg0KDQpbWGllXSBJIHdpbGwgcGxhY2Ug dGhlc2UgY2hhbmdlIGludG8gYSBwYXRjaC4gDQoNCj4gDQo+IC1TY290dA0KPiANCg0K ^ permalink raw reply [flat|nested] 14+ messages in thread
* Re: [PATCH V4 1/3] powerpc/85xx: Add QE common init functions 2013-09-25 9:51 ` Xie Xiaobo-R63061 @ 2013-09-25 18:01 ` Scott Wood 0 siblings, 0 replies; 14+ messages in thread From: Scott Wood @ 2013-09-25 18:01 UTC (permalink / raw) To: Xie Xiaobo-R63061; +Cc: Wood Scott-B07421, linuxppc-dev@lists.ozlabs.org On Wed, 2013-09-25 at 04:51 -0500, Xie Xiaobo-R63061 wrote: > > -----Original Message----- > > From: Wood Scott-B07421 > > Sent: Wednesday, September 25, 2013 7:13 AM > > To: Xie Xiaobo-R63061 > > Cc: linuxppc-dev@lists.ozlabs.org > > Subject: Re: [PATCH V4 1/3] powerpc/85xx: Add QE common init functions > > > > On Tue, 2013-09-24 at 18:48 +0800, Xie Xiaobo wrote: > > > Define two QE init functions in common file, and avoid the same codes > > > being duplicated in board files. > > > > > > Signed-off-by: Xie Xiaobo <X.Xie@freescale.com> > > > --- > > > V4 -> V3: Nochange > > > > > > arch/powerpc/platforms/85xx/common.c | 51 > > > +++++++++++++++++++++++++++++++++++ > > > arch/powerpc/platforms/85xx/mpc85xx.h | 8 ++++++ > > > 2 files changed, 59 insertions(+) > > > > > > diff --git a/arch/powerpc/platforms/85xx/common.c > > > b/arch/powerpc/platforms/85xx/common.c > > > index d0861a0..08fff48 100644 > > > --- a/arch/powerpc/platforms/85xx/common.c > > > +++ b/arch/powerpc/platforms/85xx/common.c > > > @@ -7,6 +7,9 @@ > > > */ > > > #include <linux/of_platform.h> > > > > > > +#include <asm/machdep.h> > > > +#include <asm/qe.h> > > > +#include <asm/qe_ic.h> > > > #include <sysdev/cpm2_pic.h> > > > > > > #include "mpc85xx.h" > > > @@ -80,3 +83,51 @@ void __init mpc85xx_cpm2_pic_init(void) > > > irq_set_chained_handler(irq, cpm2_cascade); } #endif > > > + > > > +#ifdef CONFIG_QUICC_ENGINE > > > +void __init mpc85xx_qe_pic_init(void) { > > > + struct device_node *np; > > > + > > > + np = of_find_compatible_node(NULL, NULL, "fsl,qe-ic"); > > > + if (np) { > > > + if (machine_is(mpc8568_mds) || machine_is(mpc8569_mds)) > > > + qe_ic_init(np, 0, qe_ic_cascade_muxed_mpic, NULL); > > > + else > > > + qe_ic_init(np, 0, qe_ic_cascade_low_mpic, > > > + qe_ic_cascade_high_mpic); > > > + of_node_put(np); > > > + } else > > > + pr_err("%s: Could not find qe-ic node\n", __func__); } > > > > Have the caller pass in a flag indicating the type of cascade. Or, > > perhaps this function isn't worth factoring out. Where is the check for > > p1021_mds? Where did 8568/9 MDS come from? I don't see those checks > > removed in patch 2. > > [Xie] The qe_pic_init just call one function qe_ic_init(), So I just need factor out the qe_init function, Is it feasible? "Or, perhaps this function isn't worth factoring out." :-) -Scott ^ permalink raw reply [flat|nested] 14+ messages in thread
end of thread, other threads:[~2013-11-06 2:32 UTC | newest] Thread overview: 14+ messages (download: mbox.gz follow: Atom feed -- links below jump to the message on this page -- 2013-09-24 10:48 [PATCH V4 1/3] powerpc/85xx: Add QE common init functions Xie Xiaobo 2013-09-24 10:48 ` [PATCH V4 2/3] powerpc/85xx: Use common init functions for QE Xie Xiaobo 2013-09-24 10:48 ` [PATCH V4 3/3] powerpc/85xx: Add TWR-P1025 board support Xie Xiaobo 2013-09-24 23:22 ` Scott Wood 2013-09-25 9:50 ` Xie Xiaobo-R63061 2013-09-25 23:09 ` Scott Wood 2013-09-26 9:27 ` Xie Xiaobo-R63061 2013-09-26 21:27 ` Scott Wood 2013-11-06 2:31 ` Xiaobo Xie 2013-09-27 17:03 ` Scott Wood 2013-10-25 9:49 ` Xie Xiaobo-R63061 2013-09-24 23:13 ` [PATCH V4 1/3] powerpc/85xx: Add QE common init functions Scott Wood 2013-09-25 9:51 ` Xie Xiaobo-R63061 2013-09-25 18:01 ` Scott Wood
This is a public inbox, see mirroring instructions for how to clone and mirror all data and code used for this inbox; as well as URLs for NNTP newsgroup(s).