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From: Scott Wood <scottwood@freescale.com>
To: Kumar Gala <galak@kernel.crashing.org>
Cc: Tiejun Chen <tiejun.chen@windriver.com>, linuxppc-dev@ozlabs.org
Subject: Re: [RFC][PATCH] powerpc/CoreNet64: compile with CONFIG_E{5,6}500_CPU well
Date: Wed, 20 Nov 2013 16:03:16 -0600	[thread overview]
Message-ID: <1384984996.1403.430.camel@snotra.buserror.net> (raw)
In-Reply-To: <CC3170D1-8CF3-4A84-B585-BC753023DE6E@kernel.crashing.org>

On Wed, 2013-11-20 at 12:47 -0600, Kumar Gala wrote:
> On Nov 20, 2013, at 10:41 AM, Scott Wood <scottwood@freescale.com> wrot=
e:
>=20
> > On Wed, 2013-11-20 at 16:35 +0800, Tiejun Chen wrote:
> >> CONFIG_ALTIVEC is always enabled for CoreNet64.
> >=20
> > In the defconfig perhaps, but this isn't a generally true statement.
> >=20
> >> And if we select CONFIG_E{5,6}500_CPU this may introduce -mcpu=3De50=
0mc64
> >> into $CFLAGS. But Altivec and Spe options not allowed with
> >> e500mc64, so :
> >=20
> > Sigh.
> >=20
> >>  CC      arch/powerpc/lib/xor_vmx.o
> >> arch/powerpc/lib/xor_vmx.c:1:0: error: AltiVec not supported in this=
 target
> >> make[1]: *** [arch/powerpc/lib/xor_vmx.o] Error 1
> >> make: *** [arch/powerpc/lib] Error 2
> >>=20
> >> Signed-off-by: Tiejun Chen <tiejun.chen@windriver.com>
> >> ---
> >> arch/powerpc/lib/Makefile |    3 +++
> >> 1 file changed, 3 insertions(+)
> >>=20
> >> diff --git a/arch/powerpc/lib/Makefile b/arch/powerpc/lib/Makefile
> >> index 95a20e1..641a77d 100644
> >> --- a/arch/powerpc/lib/Makefile
> >> +++ b/arch/powerpc/lib/Makefile
> >> @@ -40,5 +40,8 @@ obj-y			+=3D code-patching.o
> >> obj-y			+=3D feature-fixups.o
> >> obj-$(CONFIG_FTR_FIXUP_SELFTEST) +=3D feature-fixups-test.o
> >>=20
> >> +# Altivec and Spe options not allowed with e500mc64 in GCC.
> >> +ifeq ($(call cc-option-yn,-mcpu=3De500mc64),n)
> >> obj-$(CONFIG_ALTIVEC)	+=3D xor_vmx.o
> >> CFLAGS_xor_vmx.o +=3D -maltivec -mabi=3Daltivec
> >> +endif
> >=20
> > This does not seem like the right fix.  What if GCC supports both
> > -mcpu=3De500mc64 and -mcpu=3De6500, and we're using the latter?  Or f=
or that
> > matter, if we're using -mcpu=3Dwhatever-ibm-chip-has-this?
> >=20
> > Plus, wouldn't you need to do something to prevent code in that file
> > from being called?
> >=20
> > -Scott
>=20
> Why does -mcpu=3De500mc64 get you spe enabled?  It shouldn=E2=80=99t as=
 no e500mc or greater part has spe.  Can you try using -mno-spe -maltivec=
?

I don't think SPE is relevant.  The problem is that GCC refuses to allow
-maltivec to be combined with -mcpu=3De500mc64.  -mno-spe doesn't make a
difference.

-Scott

  reply	other threads:[~2013-11-20 22:03 UTC|newest]

Thread overview: 6+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2013-11-20  8:35 [RFC][PATCH] powerpc/CoreNet64: compile with CONFIG_E{5, 6}500_CPU well Tiejun Chen
2013-11-20 16:41 ` [RFC][PATCH] powerpc/CoreNet64: compile with CONFIG_E{5,6}500_CPU well Scott Wood
2013-11-20 18:47   ` [RFC][PATCH] powerpc/CoreNet64: compile with CONFIG_E{5, 6}500_CPU well Kumar Gala
2013-11-20 22:03     ` Scott Wood [this message]
2013-11-21  8:59   ` "“tiejun.chen”"
2013-11-21 17:42     ` [RFC][PATCH] powerpc/CoreNet64: compile with CONFIG_E{5,6}500_CPU well Scott Wood

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