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* [PATCH v4 1/3] powerpc: add barrier after writing kernel PTE
@ 2014-01-09  1:32 Scott Wood
  2014-01-09  1:32 ` [PATCH v4 2/3] powerpc/e6500: TLB miss handler with hardware tablewalk support Scott Wood
  2014-01-09  1:32 ` [PATCH v4 3/3] powerpc/fsl-book3e-64: Use paca for hugetlb TLB1 entry selection Scott Wood
  0 siblings, 2 replies; 3+ messages in thread
From: Scott Wood @ 2014-01-09  1:32 UTC (permalink / raw)
  To: linuxppc-dev; +Cc: Scott Wood

There is no barrier between something like ioremap() writing to
a PTE, and returning the value to a caller that may then store the
pointer in a place that is visible to other CPUs.  Such callers
generally don't perform barriers of their own.

Even if callers of ioremap() and similar things did use barriers,
the most logical choise would be smp_wmb(), which is not
architecturally sufficient when BookE hardware tablewalk is used.  A
full sync is specified by the architecture.

For userspace mappings, OTOH, we generally already have an lwsync due
to locking, and if we occasionally take a spurious fault due to not
having a full sync with hardware tablewalk, it will not be fatal
because we will retry rather than oops.

Signed-off-by: Scott Wood <scottwood@freescale.com>
---
v4: no change

 arch/powerpc/mm/pgtable_32.c |  1 +
 arch/powerpc/mm/pgtable_64.c | 12 ++++++++++++
 2 files changed, 13 insertions(+)

diff --git a/arch/powerpc/mm/pgtable_32.c b/arch/powerpc/mm/pgtable_32.c
index 5b96017..343a87f 100644
--- a/arch/powerpc/mm/pgtable_32.c
+++ b/arch/powerpc/mm/pgtable_32.c
@@ -299,6 +299,7 @@ int map_page(unsigned long va, phys_addr_t pa, int flags)
 		set_pte_at(&init_mm, va, pg, pfn_pte(pa >> PAGE_SHIFT,
 						     __pgprot(flags)));
 	}
+	smp_wmb();
 	return err;
 }
 
diff --git a/arch/powerpc/mm/pgtable_64.c b/arch/powerpc/mm/pgtable_64.c
index 02e8681..7551382 100644
--- a/arch/powerpc/mm/pgtable_64.c
+++ b/arch/powerpc/mm/pgtable_64.c
@@ -153,6 +153,18 @@ int map_kernel_page(unsigned long ea, unsigned long pa, int flags)
 		}
 #endif /* !CONFIG_PPC_MMU_NOHASH */
 	}
+
+#ifdef CONFIG_PPC_BOOK3E_64
+	/*
+	 * With hardware tablewalk, a sync is needed to ensure that
+	 * subsequent accesses see the PTE we just wrote.  Unlike userspace
+	 * mappings, we can't tolerate spurious faults, so make sure
+	 * the new PTE will be seen the first time.
+	 */
+	mb();
+#else
+	smp_wmb();
+#endif
 	return 0;
 }
 
-- 
1.8.3.2

^ permalink raw reply related	[flat|nested] 3+ messages in thread
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2014-01-09  1:32 [PATCH v4 1/3] powerpc: add barrier after writing kernel PTE Scott Wood
2014-01-09  1:32 ` [PATCH v4 2/3] powerpc/e6500: TLB miss handler with hardware tablewalk support Scott Wood
2014-01-09  1:32 ` [PATCH v4 3/3] powerpc/fsl-book3e-64: Use paca for hugetlb TLB1 entry selection Scott Wood

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