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Subject: Re: [PATCH v9] clk: corenet: Adds the clock binding
From: Scott Wood <scottwood@freescale.com>
To: Tang Yuantian <Yuantian.Tang@freescale.com>
Date: Fri, 17 Jan 2014 19:06:27 -0600
In-Reply-To: <1389600995-28293-1-git-send-email-Yuantian.Tang@freescale.com>
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On Mon, 2014-01-13 at 16:16 +0800, Tang Yuantian wrote:
> +Example for clock block and clock provider:
> +/ {
> +	clockgen: global-utilities@e1000 {
> +		compatible = "fsl,p5020-clockgen", "fsl,qoriq-clockgen-1.0";
> +		ranges = <0x0 0xe1000 0x1000>;
> +		clock-frequency = 133333;

Missing <> around 133333, and the actual p5020ds input clock (based on
observing what U-Boot fills in) is 133333333, not 133333.

I'll fix when applying.

-Scott