Re: [PATCH] clk: corenet: Update the clock bindings

[Scott Wood <scottwood@freescale.com>]

On Thu, 2014-01-23 at 20:33 -0600, Tang Yuantian-B29983 wrote:
> > > > Instead, how about a note like this near the top of the file:
> > > >
> > > > All references to "1.0" and "2.0" refer to the QorIQ chassis version
> > > > to which the chip complies.
> > > >
> > > > Chassis Version		Example Chips
> > > > ---------------		-------------
> > > > 1.0			p4080, p5020, p5040
> > > > 2.0			t4240, b4860, t1040
> > > >
> > > Better, I will update.
> > >
> > > >
> > > > BTW, this binding and the associated driver really should be called
> > > > "qoriq-clock", not "corenet-clock".  This would match the compatible
> > > > string, and it doesn't really have much to do with corenet (which is
> > > > part of the QorIQ chassis v1 and v2, but not *this* part).  Do you
> > > > know if the chassis v3 clock interface will be similar enough to
> > share a driver?
> > > >
> > > Doesn't QorIQ include some low-end socs, like p1022, p1020?
> > 
> > Yes, but those aren't "QorIQ Chassis 1.0" or "QorIQ Chassis 2.0".
> > They're mpc85xx-family chips.
> > 
> > In any case, if "qoriq" makes sense for the compatible, I don't see why
> > it doesn't make sense for the driver.
> > 
> So, "Corenet" is appropriate for driver.
> If something should change, that must be compatible string.

No.  Corenet is a bus interconnect, not a chip family (despite abuse of
the name in other contexts in Linux/U-Boot).  And the binding with qoriq
has already been accepted.

-Scott