[PATCH 0/2] Fixes for PCI-E link speed

[PATCH 0/2] Fixes for PCI-E link speed

[Kleber Sacilotto de Souza]

These two patches fix problems on the PCI-E link speed detection.
The first one fixes a regression and adds some improvements on the
code, and the second one adds definitions for Gen3 speeds.

Kleber Sacilotto de Souza (2):
  powerpc/pseries: fix regression on PCI link speed
  powerpc/pseries: add Gen3 definitions for PCIE link speed

 arch/powerpc/platforms/pseries/pci.c |   22 +++++++++++++++-------
 1 files changed, 15 insertions(+), 7 deletions(-)

[PATCH 1/2] powerpc/pseries: fix regression on PCI link speed

[Kleber Sacilotto de Souza]

Commit 5091f0c (powerpc/pseries: Fix PCIE link speed endian issue)
introduced a regression on the PCI link speed detection using the
device-tree property. The ibm,pcie-link-speed-stats property is composed
of two 32-bit integers, the first one being the maxinum link speed and
the second the current link speed. The changes introduced by the
aforementioned commit are considering just the first integer.

Fix this issue by changing how the property is accessed, using the
helper functions to properly access the array of values. The explicit
byte swapping is not needed anymore here, since it's done by the helper
functions.

Signed-off-by: Kleber Sacilotto de Souza <klebers@linux.vnet.ibm.com>
---
 arch/powerpc/platforms/pseries/pci.c |   16 +++++++++-------
 1 files changed, 9 insertions(+), 7 deletions(-)

diff --git a/arch/powerpc/platforms/pseries/pci.c b/arch/powerpc/platforms/pseries/pci.c
index 70670a2..a6f7a14 100644
--- a/arch/powerpc/platforms/pseries/pci.c
+++ b/arch/powerpc/platforms/pseries/pci.c
@@ -113,7 +113,8 @@ int pseries_root_bridge_prepare(struct pci_host_bridge *bridge)
 {
 	struct device_node *dn, *pdn;
 	struct pci_bus *bus;
-	const __be32 *pcie_link_speed_stats;
+	u32 pcie_link_speed_stats[2];
+	int rc;
 
 	bus = bridge->bus;
 
@@ -122,20 +123,21 @@ int pseries_root_bridge_prepare(struct pci_host_bridge *bridge)
 		return 0;
 
 	for (pdn = dn; pdn != NULL; pdn = of_get_next_parent(pdn)) {
-		pcie_link_speed_stats = of_get_property(pdn,
-			"ibm,pcie-link-speed-stats", NULL);
-		if (pcie_link_speed_stats)
+		rc = of_property_read_u32_array(pdn,
+				"ibm,pcie-link-speed-stats",
+				&pcie_link_speed_stats[0], 2);
+		if (!rc)
 			break;
 	}
 
 	of_node_put(pdn);
 
-	if (!pcie_link_speed_stats) {
+	if (rc) {
 		pr_err("no ibm,pcie-link-speed-stats property\n");
 		return 0;
 	}
 
-	switch (be32_to_cpup(pcie_link_speed_stats)) {
+	switch (pcie_link_speed_stats[0]) {
 	case 0x01:
 		bus->max_bus_speed = PCIE_SPEED_2_5GT;
 		break;
@@ -147,7 +149,7 @@ int pseries_root_bridge_prepare(struct pci_host_bridge *bridge)
 		break;
 	}
 
-	switch (be32_to_cpup(pcie_link_speed_stats)) {
+	switch (pcie_link_speed_stats[1]) {
 	case 0x01:
 		bus->cur_bus_speed = PCIE_SPEED_2_5GT;
 		break;
-- 
1.7.1

[PATCH 2/2] powerpc/pseries: add Gen3 definitions for PCIE link speed

[Kleber Sacilotto de Souza]

Rev3 of the PCI Express Base Specification defines a Supported Link
Speeds Vector where the bit definitions within this field are:

Bit 0 - 2.5 GT/s
Bit 1 - 5.0 GT/s
Bit 2 - 8.0 GT/s

This vector definition is used by the platform firmware to export the
maximum and current link speeds of the PCI bus via the
"ibm,pcie-link-speed-stats" device-tree property.

This patch updates pseries_root_bridge_prepare() to detect Gen3
speed buses (defined by 0x04).

Signed-off-by: Kleber Sacilotto de Souza <klebers@linux.vnet.ibm.com>
---
 arch/powerpc/platforms/pseries/pci.c |    6 ++++++
 1 files changed, 6 insertions(+), 0 deletions(-)

diff --git a/arch/powerpc/platforms/pseries/pci.c b/arch/powerpc/platforms/pseries/pci.c
index a6f7a14..c413ec1 100644
--- a/arch/powerpc/platforms/pseries/pci.c
+++ b/arch/powerpc/platforms/pseries/pci.c
@@ -144,6 +144,9 @@ int pseries_root_bridge_prepare(struct pci_host_bridge *bridge)
 	case 0x02:
 		bus->max_bus_speed = PCIE_SPEED_5_0GT;
 		break;
+	case 0x04:
+		bus->max_bus_speed = PCIE_SPEED_8_0GT;
+		break;
 	default:
 		bus->max_bus_speed = PCI_SPEED_UNKNOWN;
 		break;
@@ -156,6 +159,9 @@ int pseries_root_bridge_prepare(struct pci_host_bridge *bridge)
 	case 0x02:
 		bus->cur_bus_speed = PCIE_SPEED_5_0GT;
 		break;
+	case 0x04:
+		bus->cur_bus_speed = PCIE_SPEED_8_0GT;
+		break;
 	default:
 		bus->cur_bus_speed = PCI_SPEED_UNKNOWN;
 		break;
-- 
1.7.1

Re: [PATCH 0/2] Fixes for PCI-E link speed

[Kleber Sacilotto de Souza]

On 01/17/2014 11:56 AM, Kleber Sacilotto de Souza wrote:
> These two patches fix problems on the PCI-E link speed detection.
> The first one fixes a regression and adds some improvements on the
> code, and the second one adds definitions for Gen3 speeds.
>
> Kleber Sacilotto de Souza (2):
>    powerpc/pseries: fix regression on PCI link speed
>    powerpc/pseries: add Gen3 definitions for PCIE link speed
>
>   arch/powerpc/platforms/pseries/pci.c |   22 +++++++++++++++-------
>   1 files changed, 15 insertions(+), 7 deletions(-)
>

Hi,

Any feedback on this patch series?


Thanks,

-- 
Kleber Sacilotto de Souza
IBM Linux Technology Center

Re: [PATCH 0/2] Fixes for PCI-E link speed

[Benjamin Herrenschmidt]

On Fri, 2014-01-31 at 10:20 -0200, Kleber Sacilotto de Souza wrote:
> On 01/17/2014 11:56 AM, Kleber Sacilotto de Souza wrote:
> > These two patches fix problems on the PCI-E link speed detection.
> > The first one fixes a regression and adds some improvements on the
> > code, and the second one adds definitions for Gen3 speeds.
> >
> > Kleber Sacilotto de Souza (2):
> >    powerpc/pseries: fix regression on PCI link speed
> >    powerpc/pseries: add Gen3 definitions for PCIE link speed
> >
> >   arch/powerpc/platforms/pseries/pci.c |   22 +++++++++++++++-------
> >   1 files changed, 15 insertions(+), 7 deletions(-)
> >
> 
> Hi,
> 
> Any feedback on this patch series?

Patches on this list are tracked in patchwork so are generally not
"lost". Plus I was on vacation last week. So there's no need for such
pings unless much more time has elapsed. I'll probably put it in after
-rc1.

Ben.