From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from szxga03-in.huawei.com (szxga03-in.huawei.com [119.145.14.66]) (using TLSv1 with cipher RC4-SHA (128/128 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 5B5E614135E for ; Fri, 25 Apr 2014 19:26:16 +1000 (EST) From: Yijing Wang To: Bjorn Helgaas Subject: [PATCH 02/13] PCI: Introduce new pci_is_bridge() helper function Date: Fri, 25 Apr 2014 17:18:24 +0800 Message-ID: <1398417515-8740-3-git-send-email-wangyijing@huawei.com> In-Reply-To: <1398417515-8740-1-git-send-email-wangyijing@huawei.com> References: <1398417515-8740-1-git-send-email-wangyijing@huawei.com> MIME-Version: 1.0 Content-Type: text/plain Cc: Tony Luck , linux-ia64@vger.kernel.org, x86@kernel.org, linux-kernel@vger.kernel.org, Yijing Wang , sparclinux@vger.kernel.org, Thomas Gleixner , linuxppc-dev@lists.ozlabs.org, "David S. Miller" List-Id: Linux on PowerPC Developers Mail List List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , PCIe Spec define the PCI bridge is the PCI device which header type(bit 0 through 6) is 0x1(PCI bridge) or 0x2(CardBus bridge). Signed-off-by: Yijing Wang --- include/linux/pci.h | 6 ++++++ 1 files changed, 6 insertions(+), 0 deletions(-) diff --git a/include/linux/pci.h b/include/linux/pci.h index aab57b4..827077a 100644 --- a/include/linux/pci.h +++ b/include/linux/pci.h @@ -477,6 +477,12 @@ static inline bool pci_is_root_bus(struct pci_bus *pbus) return !(pbus->parent); } +static inline bool pci_is_bridge(struct pci_dev *dev) +{ + return dev->hdr_type == PCI_HEADER_TYPE_BRIDGE || + dev->hdr_type == PCI_HEADER_TYPE_CARDBUS; +} + static inline struct pci_dev *pci_upstream_bridge(struct pci_dev *dev) { dev = pci_physfn(dev); -- 1.7.1