From: Scott Wood <scottwood@freescale.com>
To: Alexander Graf <agraf@suse.de>
Cc: Mihai Caraman <mihai.caraman@freescale.com>,
David Laight <David.Laight@ACULAB.COM>,
"linuxppc-dev@lists.ozlabs.org" <linuxppc-dev@lists.ozlabs.org>,
"kvm-ppc@vger.kernel.org" <kvm-ppc@vger.kernel.org>,
"kvm@vger.kernel.org" <kvm@vger.kernel.org>
Subject: Re: [PATCH v2 4/4] KVM: PPC: Bookehv: Get vcpu's last instruction for emulation
Date: Fri, 2 May 2014 10:32:39 -0500 [thread overview]
Message-ID: <1399044759.15726.45.camel@snotra.buserror.net> (raw)
In-Reply-To: <53637D3B.4010205@suse.de>
On Fri, 2014-05-02 at 13:10 +0200, Alexander Graf wrote:
> On 05/02/2014 12:12 PM, David Laight wrote:
> > You also probably want the page mapped uncached - no point polluting the data
> > cache.
We can't do that without creating an architecturally illegal alias
between cacheable and non-cacheable mappings.
> Do e500 chips have a shared I/D cache somewhere?
Yes. Only L1 is separate.
-Scott
prev parent reply other threads:[~2014-05-02 15:32 UTC|newest]
Thread overview: 17+ messages / expand[flat|nested] mbox.gz Atom feed top
2014-05-01 0:45 [PATCH v2 0/4] KVM: PPC: Read guest instruction from kvmppc_get_last_inst() Mihai Caraman
2014-05-01 0:45 ` [PATCH v2 1/4] KVM: PPC: e500mc: Revert "add load inst fixup" Mihai Caraman
2014-05-02 9:24 ` Alexander Graf
2014-05-02 23:14 ` mihai.caraman
2014-05-03 22:14 ` Alexander Graf
2014-05-06 15:48 ` mihai.caraman
2014-05-06 15:54 ` Alexander Graf
2014-05-01 0:45 ` [PATCH v2 2/4] KVM: PPC: Book3e: Add TLBSEL/TSIZE defines for MAS0/1 Mihai Caraman
2014-05-01 0:45 ` [PATCH v2 3/4] KVM: PPC: Alow kvmppc_get_last_inst() to fail Mihai Caraman
2014-05-02 9:54 ` Alexander Graf
2014-05-06 19:06 ` mihai.caraman
2014-05-08 13:31 ` Alexander Graf
2014-05-01 0:45 ` [PATCH v2 4/4] KVM: PPC: Bookehv: Get vcpu's last instruction for emulation Mihai Caraman
2014-05-02 10:01 ` Alexander Graf
2014-05-02 10:12 ` David Laight
2014-05-02 11:10 ` Alexander Graf
2014-05-02 15:32 ` Scott Wood [this message]
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