From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from na01-bn1-obe.outbound.protection.outlook.com (dns-bn1lp0143.outbound.protection.outlook.com [207.46.163.143]) (using TLSv1 with cipher AES128-SHA (128/128 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 94FB114013F for ; Sat, 3 May 2014 09:14:37 +1000 (EST) From: "mihai.caraman@freescale.com" To: Alexander Graf Subject: RE: [PATCH v2 1/4] KVM: PPC: e500mc: Revert "add load inst fixup" Date: Fri, 2 May 2014 23:14:29 +0000 Message-ID: <1399072472827.57968@freescale.com> References: <1398905152-18091-1-git-send-email-mihai.caraman@freescale.com> <1398905152-18091-2-git-send-email-mihai.caraman@freescale.com>, <53636436.60002@suse.de> In-Reply-To: <53636436.60002@suse.de> Content-Type: text/plain; charset="us-ascii" MIME-Version: 1.0 Cc: "linuxppc-dev@lists.ozlabs.org" , "kvm@vger.kernel.org" , "kvm-ppc@vger.kernel.org" List-Id: Linux on PowerPC Developers Mail List List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , > From: Alexander Graf =0A= > Sent: Friday, May 2, 2014 12:24 PM=0A= > To: Caraman Mihai Claudiu-B02008=0A= > Cc: kvm-ppc@vger.kernel.org; kvm@vger.kernel.org; linuxppc-dev@lists.ozla= bs.org=0A= > Subject: Re: [PATCH v2 1/4] KVM: PPC: e500mc: Revert "add load inst fixup= "=0A= > =0A= > On 05/01/2014 02:45 AM, Mihai Caraman wrote:=0A= > > The commit 1d628af7 "add load inst fixup" made an attempt to handle=0A= > > failures generated by reading the guest current instruction. The fixup= =0A= > > code that was added works by chance hiding the real issue.=0A= > >=0A= > > Load external pid (lwepx) instruction, used by KVM to read guest=0A= > > instructions, is executed in a subsituted guest translation context=0A= > > (EPLC[EGS] =3D 1). In consequence lwepx's TLB error and data storage=0A= > > interrupts need to be handled by KVM, even though these interrupts=0A= > > are generated from host context (MSR[GS] =3D 0).=0A= > >=0A= > > Currently, KVM hooks only interrupts generated from guest context=0A= > > (MSR[GS] =3D 1), doing minimal checks on the fast path to avoid host=0A= > > performance degradation. As a result, the host kernel handles lwepx=0A= > > faults searching the faulting guest data address (loaded in DEAR) in=0A= > > its own Logical Partition ID (LPID) 0 context. In case a host translati= on=0A= > > is found the execution returns to the lwepx instruction instead of the= =0A= > > fixup, the host ending up in an infinite loop.=0A= > >=0A= > > Revert the commit "add load inst fixup". lwepx issue will be addressed= =0A= > > in a subsequent patch without needing fixup code.=0A= > >=0A= > > Signed-off-by: Mihai Caraman =0A= > =0A= > Just a random idea: Could we just switch IVOR2 during the critical lwepx= =0A= > phase? In fact, we could even do that later when we're already in C code= =0A= > and try to recover the last instruction. The code IVOR2 would point to=0A= > would simply set the register we're trying to read to as LAST_INST_FAIL= =0A= > and rfi.=0A= =0A= This was the first idea that sprang to my mind inspired from how DO_KVM=0A= is hooked on PR. I actually did a simple POC for e500mc/e5500, but this wil= l=0A= not work on e6500 which has shared IVORs between HW threads.=0A= =0A= -Mike=