From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mail-de.keymile.com (mail-de.keymile.com [195.8.104.250]) (using TLSv1.1 with cipher ECDHE-RSA-AES256-SHA (256/256 bits)) (No client certificate requested) by lists.ozlabs.org (Postfix) with ESMTPS id DED2C1A0041 for ; Thu, 5 Jun 2014 01:40:04 +1000 (EST) From: Valentin Longchamp To: Linux PowerPC Kernel , Scott Wood Subject: [PATCH] powerpc/mpc85xx: fix fsl/p2041-post.dtsi clockgen mux2 Date: Wed, 4 Jun 2014 17:34:01 +0200 Message-Id: <1401896041-22734-1-git-send-email-valentin.longchamp@keymile.com> Cc: Linux device trees , Valentin Longchamp List-Id: Linux on PowerPC Developers Mail List List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , The mux2 node is missing the clock-output-names field that is required by the clk-ppc-corenet driver. Signed-off-by: Valentin Longchamp --- arch/powerpc/boot/dts/fsl/p2041si-post.dtsi | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/powerpc/boot/dts/fsl/p2041si-post.dtsi b/arch/powerpc/boot/dts/fsl/p2041si-post.dtsi index e2987a3..45ce43c 100644 --- a/arch/powerpc/boot/dts/fsl/p2041si-post.dtsi +++ b/arch/powerpc/boot/dts/fsl/p2041si-post.dtsi @@ -358,6 +358,7 @@ compatible = "fsl,qoriq-core-mux-1.0"; clocks = <&pll0 0>, <&pll0 1>, <&pll1 0>, <&pll1 1>; clock-names = "pll0", "pll0-div2", "pll1", "pll1-div2"; + clock-output-names = "cmux2"; }; mux3: mux3@60 { -- 1.8.0.1