From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from na01-bn1-obe.outbound.protection.outlook.com (mail-bn1blp0182.outbound.protection.outlook.com [207.46.163.182]) (using TLSv1 with cipher ECDHE-RSA-AES256-SHA (256/256 bits)) (No client certificate requested) by lists.ozlabs.org (Postfix) with ESMTPS id BA6E71A005A for ; Fri, 22 Aug 2014 20:40:41 +1000 (EST) From: Jingchang Lu To: Subject: [RESEND] clk: ppc-corenet: Add Freescale ARM-based platforms CLK_OF_DECLARE support Date: Fri, 22 Aug 2014 17:34:56 +0800 Message-ID: <1408700096-25415-1-git-send-email-jingchang.lu@freescale.com> MIME-Version: 1.0 Content-Type: text/plain Cc: linuxppc-dev@lists.ozlabs.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, Jingchang Lu List-Id: Linux on PowerPC Developers Mail List List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Signed-off-by: Jingchang Lu --- drivers/clk/Kconfig | 7 ++++--- drivers/clk/clk-ppc-corenet.c | 5 +++++ 2 files changed, 9 insertions(+), 3 deletions(-) diff --git a/drivers/clk/Kconfig b/drivers/clk/Kconfig index cfd3af7..8784704 100644 --- a/drivers/clk/Kconfig +++ b/drivers/clk/Kconfig @@ -82,11 +82,12 @@ config COMMON_CLK_AXI_CLKGEN FPGAs. It is commonly used in Analog Devices' reference designs. config CLK_PPC_CORENET - bool "Clock driver for PowerPC corenet platforms" - depends on PPC_E500MC && OF + bool "Clock driver for PowerPC corenet and compatible ARM-based platforms" + depends on (PPC_E500MC || ARM) && OF ---help--- This adds the clock driver support for Freescale PowerPC corenet - platforms using common clock framework. + platforms and compatible Freescale ARM based platforms using common + clock framework. config COMMON_CLK_XGENE bool "Clock driver for APM XGene SoC" diff --git a/drivers/clk/clk-ppc-corenet.c b/drivers/clk/clk-ppc-corenet.c index 8e58edf..7692cac 100644 --- a/drivers/clk/clk-ppc-corenet.c +++ b/drivers/clk/clk-ppc-corenet.c @@ -305,3 +305,8 @@ static int __init ppc_corenet_clk_init(void) return platform_driver_register(&ppc_corenet_clk_driver); } subsys_initcall(ppc_corenet_clk_init); + +CLK_OF_DECLARE(ppc_core_pll_v1, "fsl,qoriq-core-pll-1.0", core_pll_init); +CLK_OF_DECLARE(ppc_core_pll_v2, "fsl,qoriq-core-pll-2.0", core_pll_init); +CLK_OF_DECLARE(ppc_core_mux_v1, "fsl,qoriq-core-mux-1.0", core_mux_init); +CLK_OF_DECLARE(ppc_core_mux_v2, "fsl,qoriq-core-mux-2.0", core_mux_init); -- 1.8.0