Re: bit fields && data tearing

[James Bottomley <James.Bottomley@HansenPartnership.com>]

On Mon, 2014-09-08 at 12:12 -0700, H. Peter Anvin wrote:
> On 09/08/2014 12:09 PM, James Bottomley wrote:
> > 
> > Um, I think you need to re-read the thread; that's not what I said at
> > all. It's even written lower down: "PA can't do atomic bit sets (no
> > atomic RMW except the ldcw operation) it can do atomic writes to
> > fundamental sizes (byte, short, int, long) provided gcc emits the
> > correct primitive".  The original question was whether atomicity
> > required native bus width access, which we currently assume, so there's
> > no extant problem.
> > 
> 
> The issue at hand was whether or not partially overlapped (but natually
> aligned) writes can pass each other.  *This* is the aggressive
> relaxation to which I am referring.

I don't understand what you mean by "pass each other".  Atomicity
guarantees are not ordering guarantees in a SMP environment.  The
guarantee is that if you follow the rules when two CPUs update the same
natural width aligned object simultaneously using the same primitive,
the result is either one or the other of their updates.  Which one wins
(the ordering) isn't defined.

James


> I would guess that that is a very unusual constraint.