From: Michael Neuling <mikey@neuling.org>
To: Jeremy Kerr <jk@ozlabs.org>
Cc: cbe-oss-dev@lists.ozlabs.org, arnd@arndb.de, greg@kroah.com,
linux-kernel@vger.kernel.org, imunsie@au.ibm.com,
linuxppc-dev@ozlabs.org, anton@samba.org
Subject: Re: [PATCH 02/15] powerpc/cell: Move data segment faulting code out of cell platform
Date: Fri, 19 Sep 2014 09:45:56 +1000 [thread overview]
Message-ID: <1411083956.12154.29.camel@ale.ozlabs.ibm.com> (raw)
In-Reply-To: <541AB38B.5080706@ozlabs.org>
> > +
> > +int copro_data_segment(struct mm_struct *mm, u64 ea, u64 *esid, u64 *v=
sid)
> > +{
> > + int psize, ssize;
> > +
> > + *esid =3D (ea & ESID_MASK) | SLB_ESID_V;
> > +
> > + switch (REGION_ID(ea)) {
> > + case USER_REGION_ID:
> > + pr_devel("copro_data_segment: 0x%llx -- USER_REGION_ID\n", ea);
> > +#ifdef CONFIG_PPC_MM_SLICES
> > + psize =3D get_slice_psize(mm, ea);
> > +#else
> > + psize =3D mm->context.user_psize;
> > +#endif
> > + ssize =3D user_segment_size(ea);
> > + *vsid =3D (get_vsid(mm->context.id, ea, ssize)
> > + << slb_vsid_shift(ssize)) | SLB_VSID_USER
> > + | (ssize =3D=3D MMU_SEGSIZE_1T ? SLB_VSID_B_1T : 0);
> > + break;
> > + case VMALLOC_REGION_ID:
> > + pr_devel("copro_data_segment: 0x%llx -- VMALLOC_REGION_ID\n", ea);
> > + if (ea < VMALLOC_END)
> > + psize =3D mmu_vmalloc_psize;
> > + else
> > + psize =3D mmu_io_psize;
> > + *vsid =3D (get_kernel_vsid(ea, mmu_kernel_ssize)
> > + << SLB_VSID_SHIFT) | SLB_VSID_KERNEL
> > + | (mmu_kernel_ssize =3D=3D MMU_SEGSIZE_1T ? SLB_VSID_B_1T : 0);
> > + break;
> > + case KERNEL_REGION_ID:
> > + pr_devel("copro_data_segment: 0x%llx -- KERNEL_REGION_ID\n", ea);
> > + psize =3D mmu_linear_psize;
> > + *vsid =3D (get_kernel_vsid(ea, mmu_kernel_ssize)
> > + << SLB_VSID_SHIFT) | SLB_VSID_KERNEL
> > + | (mmu_kernel_ssize =3D=3D MMU_SEGSIZE_1T ? SLB_VSID_B_1T : 0);
> > + break;
> > + default:
> > + /* Future: support kernel segments so that drivers can use the
> > + * CoProcessors */
> > + pr_debug("invalid region access at %016llx\n", ea);
> > + return 1;
> > + }
> > + *vsid |=3D mmu_psize_defs[psize].sllp;
>=20
> A bit of a nitpick, but how about you remove the repeated:
>=20
> | (<size> =3D=3D MMU_SEGSIZE_1T ? SLB_VSID_B_1T : 0)
>=20
> then set ssize in each of the switch cases (like we do with psize), and
> or-in the VSID_B_1T bit at the end:
> =09
> *vsid |=3D mmu_psize_defs[psize].sllp
> | (ssize =3D=3D MMU_SEGSIZE_1T ? SLB_VSID_B_1T : 0);
Nice. I think below is what you mean.
I'll fold this into the existing patch and repost in a few days.
Thanks,
Mikey
diff --git a/arch/powerpc/mm/copro_fault.c b/arch/powerpc/mm/copro_fault.c
index 4105a63..939caf6 100644
--- a/arch/powerpc/mm/copro_fault.c
+++ b/arch/powerpc/mm/copro_fault.c
@@ -107,8 +107,7 @@ int copro_data_segment(struct mm_struct *mm, u64 ea, u6=
4 *esid, u64 *vsid)
#endif
ssize =3D user_segment_size(ea);
*vsid =3D (get_vsid(mm->context.id, ea, ssize)
- << slb_vsid_shift(ssize)) | SLB_VSID_USER
- | (ssize =3D=3D MMU_SEGSIZE_1T ? SLB_VSID_B_1T : 0);
+ << slb_vsid_shift(ssize)) | SLB_VSID_USER;
break;
case VMALLOC_REGION_ID:
pr_devel("copro_data_segment: 0x%llx -- VMALLOC_REGION_ID\n", ea);
@@ -116,16 +115,16 @@ int copro_data_segment(struct mm_struct *mm, u64 ea, =
u64 *esid, u64 *vsid)
psize =3D mmu_vmalloc_psize;
else
psize =3D mmu_io_psize;
+ ssize =3D mmu_kernel_ssize;
*vsid =3D (get_kernel_vsid(ea, mmu_kernel_ssize)
- << SLB_VSID_SHIFT) | SLB_VSID_KERNEL
- | (mmu_kernel_ssize =3D=3D MMU_SEGSIZE_1T ? SLB_VSID_B_1T : 0);
+ << SLB_VSID_SHIFT) | SLB_VSID_KERNEL;
break;
case KERNEL_REGION_ID:
pr_devel("copro_data_segment: 0x%llx -- KERNEL_REGION_ID\n", ea);
psize =3D mmu_linear_psize;
+ ssize =3D mmu_kernel_ssize;
*vsid =3D (get_kernel_vsid(ea, mmu_kernel_ssize)
- << SLB_VSID_SHIFT) | SLB_VSID_KERNEL
- | (mmu_kernel_ssize =3D=3D MMU_SEGSIZE_1T ? SLB_VSID_B_1T : 0);
+ << SLB_VSID_SHIFT) | SLB_VSID_KERNEL;
break;
default:
/* Future: support kernel segments so that drivers can use the
@@ -133,7 +132,8 @@ int copro_data_segment(struct mm_struct *mm, u64 ea, u6=
4 *esid, u64 *vsid)
pr_debug("invalid region access at %016llx\n", ea);
return 1;
}
- *vsid |=3D mmu_psize_defs[psize].sllp;
+ *vsid |=3D mmu_psize_defs[psize].sllp |
+ (ssize =3D=3D MMU_SEGSIZE_1T) ? SLB_VSID_B_1T : 0;
=20
return 0;
}
next prev parent reply other threads:[~2014-09-18 23:45 UTC|newest]
Thread overview: 43+ messages / expand[flat|nested] mbox.gz Atom feed top
2014-09-18 8:26 [PATCH 0/15] POWER8 Coherent Accelerator device driver Michael Neuling
2014-09-18 8:26 ` [PATCH 01/15] powerpc/cell: Move spu_handle_mm_fault() out of cell platform Michael Neuling
2014-09-18 10:00 ` Jeremy Kerr
2014-09-18 23:26 ` Michael Neuling
2014-09-26 3:57 ` Anton Blanchard
2014-09-18 8:26 ` [PATCH 02/15] powerpc/cell: Move data segment faulting code " Michael Neuling
2014-09-18 10:27 ` Jeremy Kerr
2014-09-18 23:45 ` Michael Neuling [this message]
2014-09-26 4:05 ` Anton Blanchard
2014-09-26 11:19 ` Michael Neuling
2014-09-29 8:30 ` Aneesh Kumar K.V
2014-09-30 4:40 ` Michael Neuling
2014-09-18 8:26 ` [PATCH 03/15] powerpc/msi: Improve IRQ bitmap allocator Michael Neuling
2014-09-19 20:16 ` Scott Wood
2014-09-19 20:19 ` Scott Wood
2014-09-22 8:26 ` Laurentiu Tudor
2014-09-22 23:50 ` Scott Wood
2014-09-22 8:25 ` Laurentiu Tudor
2014-09-22 8:29 ` Laurentiu Tudor
2014-09-22 22:59 ` Michael Neuling
2014-09-18 8:26 ` [PATCH 04/15] powerpc/mm: Export mmu_kernel_ssize and mmu_linear_psize Michael Neuling
2014-09-18 8:26 ` [PATCH 05/15] powerpc/powernv: Split out set MSI IRQ chip code Michael Neuling
2014-09-19 6:54 ` Gavin Shan
2014-09-22 4:31 ` Michael Neuling
2014-09-18 8:26 ` [PATCH 06/15] cxl: Add new header for call backs and structs Michael Neuling
2014-09-18 8:26 ` [PATCH 07/15] powerpc/powerpc: Add new PCIe functions for allocating cxl interrupts Michael Neuling
2014-09-19 7:09 ` Gavin Shan
2014-09-22 5:01 ` Michael Neuling
2014-09-18 8:26 ` [PATCH 08/15] powerpc/mm: Add new hash_page_mm() Michael Neuling
2014-09-29 8:50 ` Aneesh Kumar K.V
[not found] ` <1412054407.1733.77.camel@ale.ozlabs.ibm.com>
2014-09-30 6:13 ` Michael Neuling
2014-09-18 8:26 ` [PATCH 09/15] powerpc/opal: Add PHB to cxl mode call Michael Neuling
2014-09-26 4:35 ` Anton Blanchard
2014-09-18 8:26 ` [PATCH 10/15] powerpc/mm: Add hooks for cxl Michael Neuling
2014-09-26 4:33 ` Anton Blanchard
2014-09-26 11:33 ` Michael Neuling
2014-09-26 13:24 ` Anton Blanchard
2014-09-29 9:10 ` Aneesh Kumar K.V
2014-09-18 8:26 ` [PATCH 11/15] cxl: Add base builtin support Michael Neuling
2014-09-18 8:26 ` [PATCH 12/15] cxl: Driver code for powernv PCIe based cards for userspace access Michael Neuling
2014-09-18 8:26 ` [PATCH 13/15] cxl: Userspace header file Michael Neuling
2014-09-18 8:26 ` [PATCH 14/15] cxl: Add driver to Kbuild and Makefiles Michael Neuling
2014-09-18 8:27 ` [PATCH 15/15] cxl: Add documentation for userspace APIs Michael Neuling
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