* [PATCH 3/3] ls1021a-twr/qe: add qe node to ls1-twr
@ 2014-10-10 6:49 Zhao Qiang
2014-10-10 18:08 ` Scott Wood
0 siblings, 1 reply; 2+ messages in thread
From: Zhao Qiang @ 2014-10-10 6:49 UTC (permalink / raw)
To: linuxppc-dev, linux-arm-kernel, devicetree, B07421; +Cc: Zhao Qiang, R63061
add qe node to ls1021atwr fdt.
Signed-off-by: Zhao Qiang <B45475@freescale.com>
---
arch/arm/boot/dts/ls1021a-twr.dts | 24 +++++++++++++++
arch/arm/boot/dts/ls1021a.dtsi | 64 +++++++++++++++++++++++++++++++++++++++
2 files changed, 88 insertions(+)
diff --git a/arch/arm/boot/dts/ls1021a-twr.dts b/arch/arm/boot/dts/ls1021a-twr.dts
index a52be7b..415387f 100755
--- a/arch/arm/boot/dts/ls1021a-twr.dts
+++ b/arch/arm/boot/dts/ls1021a-twr.dts
@@ -164,6 +164,30 @@
};
};
+&uqe {
+ tdma: ucc@2000 {
+ compatible = "fsl,ucc-tdm";
+ rx-clock-name = "clk8";
+ tx-clock-name = "clk9";
+ fsl,rx-sync-clock = "rsync_pin";
+ fsl,tx-sync-clock = "tsync_pin";
+ fsl,tx-timeslot = <0xfffffffe>;
+ fsl,rx-timeslot = <0xfffffffe>;
+ fsl,tdm-framer-type = "e1";
+ fsl,tdm-mode = "normal";
+ fsl,tdm-id = <0>;
+ fsl,siram-entry-id = <0>;
+ };
+
+ serial: ucc@2200 {
+ device_type = "serial";
+ compatible = "ucc_uart";
+ port-number = <1>;
+ rx-clock-name = "brg2";
+ tx-clock-name = "brg2";
+ };
+};
+
&pwm6 {
status = "okay";
};
diff --git a/arch/arm/boot/dts/ls1021a.dtsi b/arch/arm/boot/dts/ls1021a.dtsi
index 80747dc..3f2ab89 100644
--- a/arch/arm/boot/dts/ls1021a.dtsi
+++ b/arch/arm/boot/dts/ls1021a.dtsi
@@ -314,6 +314,70 @@
status = "disabled";
};
+ uqe: uqe@2400000 {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ device_type = "qe";
+ compatible = "fsl,qe", "simple-bus";
+ ranges = <0x0 0x0 0x2400000 0x40000>;
+ reg = <0x0 0x2400000 0x0 0x480>;
+ brg-frequency = <100000000>;
+ bus-frequency = <200000000>;
+
+ fsl,qe-num-riscs = <1>;
+ fsl,qe-num-snums = <28>;
+
+ qeic: qeic@80 {
+ compatible = "fsl,qe-ic";
+ reg = <0x80 0x80>;
+ #address-cells = <0>;
+ interrupt-controller;
+ #interrupt-cells = <1>;
+ interrupts = <0 109 0x04 0 109 0x04>;
+ };
+
+ si1: si@700 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ compatible = "fsl,qe-si";
+ reg = <0x700 0x80>;
+ };
+
+ siram1: siram@1000 {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ compatible = "fsl,qe-siram";
+ reg = <0x1000 0x800>;
+ };
+
+ ucc@2000 {
+ cell-index = <1>;
+ reg = <0x2000 0x200>;
+ interrupts = <32>;
+ interrupt-parent = <&qeic>;
+ };
+
+ ucc@2200 {
+ cell-index = <3>;
+ reg = <0x2200 0x200>;
+ interrupts = <34>;
+ interrupt-parent = <&qeic>;
+ };
+
+ muram@10000 {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ compatible = "fsl,qe-muram", "fsl,cpm-muram";
+ ranges = <0x0 0x10000 0x6000>;
+
+ data-only@0 {
+ compatible = "fsl,qe-muram-data",
+ "fsl,cpm-muram-data";
+ reg = <0x0 0x6000>;
+ };
+ };
+ };
+
lpuart0: serial@2950000 {
compatible = "fsl,ls1021a-lpuart";
reg = <0x0 0x2950000 0x0 0x1000>;
--
2.1.0.27.g96db324
^ permalink raw reply related [flat|nested] 2+ messages in thread
* Re: [PATCH 3/3] ls1021a-twr/qe: add qe node to ls1-twr
2014-10-10 6:49 [PATCH 3/3] ls1021a-twr/qe: add qe node to ls1-twr Zhao Qiang
@ 2014-10-10 18:08 ` Scott Wood
0 siblings, 0 replies; 2+ messages in thread
From: Scott Wood @ 2014-10-10 18:08 UTC (permalink / raw)
To: Zhao Qiang; +Cc: devicetree, R63061, linuxppc-dev, linux-arm-kernel, B07421
On Fri, 2014-10-10 at 14:49 +0800, Zhao Qiang wrote:
> add qe node to ls1021atwr fdt.
>
> Signed-off-by: Zhao Qiang <B45475@freescale.com>
> ---
> arch/arm/boot/dts/ls1021a-twr.dts | 24 +++++++++++++++
> arch/arm/boot/dts/ls1021a.dtsi | 64 +++++++++++++++++++++++++++++++++++++++
> 2 files changed, 88 insertions(+)
>
> diff --git a/arch/arm/boot/dts/ls1021a-twr.dts b/arch/arm/boot/dts/ls1021a-twr.dts
> index a52be7b..415387f 100755
> --- a/arch/arm/boot/dts/ls1021a-twr.dts
> +++ b/arch/arm/boot/dts/ls1021a-twr.dts
> @@ -164,6 +164,30 @@
> };
> };
>
> +&uqe {
> + tdma: ucc@2000 {
> + compatible = "fsl,ucc-tdm";
Binding?
> + rx-clock-name = "clk8";
> + tx-clock-name = "clk9";
> + fsl,rx-sync-clock = "rsync_pin";
> + fsl,tx-sync-clock = "tsync_pin";
> + fsl,tx-timeslot = <0xfffffffe>;
> + fsl,rx-timeslot = <0xfffffffe>;
> + fsl,tdm-framer-type = "e1";
> + fsl,tdm-mode = "normal";
> + fsl,tdm-id = <0>;
> + fsl,siram-entry-id = <0>;
> + };
> +
> + serial: ucc@2200 {
> + device_type = "serial";
> + compatible = "ucc_uart";
> + port-number = <1>;
> + rx-clock-name = "brg2";
> + tx-clock-name = "brg2";
> + };
Binding for ucc_uart? Why device_type?
> +};
> +
> &pwm6 {
> status = "okay";
> };
> diff --git a/arch/arm/boot/dts/ls1021a.dtsi b/arch/arm/boot/dts/ls1021a.dtsi
> index 80747dc..3f2ab89 100644
> --- a/arch/arm/boot/dts/ls1021a.dtsi
> +++ b/arch/arm/boot/dts/ls1021a.dtsi
> @@ -314,6 +314,70 @@
> status = "disabled";
> };
>
> + uqe: uqe@2400000 {
How does "uqe" differ from "qe"?
-Scott
^ permalink raw reply [flat|nested] 2+ messages in thread
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