From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from szxga02-in.huawei.com (szxga02-in.huawei.com [119.145.14.65]) (using TLSv1 with cipher RC4-SHA (128/128 bits)) (No client certificate requested) by lists.ozlabs.org (Postfix) with ESMTPS id AAD421A177C for ; Mon, 27 Oct 2014 23:44:09 +1100 (AEDT) From: Yijing Wang To: Bjorn Helgaas Subject: [PATCH 09/16] MIPS/Xlr/MSI: Use MSI controller framework to configure MSI/MSI-X irq Date: Mon, 27 Oct 2014 21:22:15 +0800 Message-ID: <1414416142-31239-10-git-send-email-wangyijing@huawei.com> In-Reply-To: <1414416142-31239-1-git-send-email-wangyijing@huawei.com> References: <1414416142-31239-1-git-send-email-wangyijing@huawei.com> MIME-Version: 1.0 Content-Type: text/plain Cc: linux-mips@linux-mips.org, linux-ia64@vger.kernel.org, linux-pci@vger.kernel.org, Xinwei Hu , Yijing Wang , Thierry Reding , sparclinux@vger.kernel.org, linux-s390@vger.kernel.org, Russell King , Joerg Roedel , x86@kernel.org, Sebastian Ott , xen-devel@lists.xenproject.org, Konrad Rzeszutek Wilk , Chris Metcalf , Thomas Gleixner , linux-arm-kernel@lists.infradead.org, Thomas Petazzoni , Tony Luck , Sergei Shtylyov , linux-kernel@vger.kernel.org, Ralf Baechle , iommu@lists.linux-foundation.org, David Vrabel , Wuyun , linuxppc-dev@lists.ozlabs.org, "David S. Miller" , Lucas Stach List-Id: Linux on PowerPC Developers Mail List List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Use MSI controller framework instead of arch MSI functions to configure MSI/MSI-X irq. So we can manage MSI/MSI-X irq in a unified framework. Signed-off-by: Yijing Wang --- arch/mips/pci/pci-xlr.c | 17 +++++++++++++++-- 1 files changed, 15 insertions(+), 2 deletions(-) diff --git a/arch/mips/pci/pci-xlr.c b/arch/mips/pci/pci-xlr.c index 0dde803..1e43c70 100644 --- a/arch/mips/pci/pci-xlr.c +++ b/arch/mips/pci/pci-xlr.c @@ -149,6 +149,8 @@ static struct resource nlm_pci_io_resource = { .flags = IORESOURCE_IO, }; +static struct msi_controller xlr_msi_ctrl; + struct pci_controller nlm_pci_controller = { .index = 0, .pci_ops = &nlm_pci_ops, @@ -156,6 +158,9 @@ struct pci_controller nlm_pci_controller = { .mem_offset = 0x00000000UL, .io_resource = &nlm_pci_io_resource, .io_offset = 0x00000000UL, +#ifdef CONFIG_PCI_MSI + .msi_ctrl = &xlr_msi_ctrl, +#endif }; /* @@ -214,11 +219,13 @@ static int get_irq_vector(const struct pci_dev *dev) } #ifdef CONFIG_PCI_MSI -void arch_teardown_msi_irq(unsigned int irq) +static void xlr_teardown_msi_irq(struct msi_controller *ctrl, + unsigned int irq) { } -int arch_setup_msi_irq(struct pci_dev *dev, struct msi_desc *desc) +static int xlr_setup_msi_irq(struct msi_controller *ctrl, + struct pci_dev *dev, struct msi_desc *desc) { struct msi_msg msg; struct pci_dev *lnk; @@ -263,6 +270,12 @@ int arch_setup_msi_irq(struct pci_dev *dev, struct msi_desc *desc) write_msi_msg(irq, &msg); return 0; } + +static struct msi_controller xlr_msi_ctrl = { + .setup_irq = xlr_setup_msi_irq, + .teardown_irq = xlr_teardown_msi_irq, +}; + #endif /* Extra ACK needed for XLR on chip PCI controller */ -- 1.7.1