From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from ozlabs.org (ozlabs.org [IPv6:2401:3900:2:1::2]) (using TLSv1.2 with cipher AECDH-AES256-SHA (256/256 bits)) (No client certificate requested) by lists.ozlabs.org (Postfix) with ESMTPS id 5F8671A0B76 for ; Thu, 4 Dec 2014 16:51:05 +1100 (AEDT) Received: from e23smtp09.au.ibm.com (e23smtp09.au.ibm.com [202.81.31.142]) (using TLSv1 with cipher DHE-RSA-AES256-SHA (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 3109D1400E2 for ; Thu, 4 Dec 2014 16:51:05 +1100 (AEDT) Received: from /spool/local by e23smtp09.au.ibm.com with IBM ESMTP SMTP Gateway: Authorized Use Only! Violators will be prosecuted for from ; Thu, 4 Dec 2014 15:51:04 +1000 Received: from d23relay08.au.ibm.com (d23relay08.au.ibm.com [9.185.71.33]) by d23dlp03.au.ibm.com (Postfix) with ESMTP id 6D3A1357805D for ; Thu, 4 Dec 2014 16:51:02 +1100 (EST) Received: from d23av04.au.ibm.com (d23av04.au.ibm.com [9.190.235.139]) by d23relay08.au.ibm.com (8.14.9/8.14.9/NCO v10.0) with ESMTP id sB45p2LT30539962 for ; Thu, 4 Dec 2014 16:51:02 +1100 Received: from d23av04.au.ibm.com (localhost [127.0.0.1]) by d23av04.au.ibm.com (8.14.4/8.14.4/NCO v10.0 AVout) with ESMTP id sB45p1dc010523 for ; Thu, 4 Dec 2014 16:51:01 +1100 From: Gavin Shan To: linuxppc-dev@ozlabs.org Subject: [PATCH 3/3] powerpc/powernv: Issue fundamental reset if required Date: Thu, 4 Dec 2014 16:50:53 +1100 Message-Id: <1417672253-26692-4-git-send-email-gwshan@linux.vnet.ibm.com> In-Reply-To: <1417672253-26692-1-git-send-email-gwshan@linux.vnet.ibm.com> References: <1417672253-26692-1-git-send-email-gwshan@linux.vnet.ibm.com> Cc: Gavin Shan List-Id: Linux on PowerPC Developers Mail List List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Function pnv_pci_reset_secondary_bus() is used to reset specified PCI bus, which is leaded by root complex or PCI bridge. That means the function shouldn't be called on PCI root bus and the patch removes the logic for the case. Also, some adapters may require fundamental reset to reload their firmwares. Otherwise, they will fail to load their firmwares and those adapters can't work properly after reset, as being reported in VFIO pass-through scenario. The patch checks the reset type required by the child adapters of the PCI bus and issue fundamental reset if necessary. Signed-off-by: Gavin Shan --- arch/powerpc/platforms/powernv/eeh-ioda.c | 34 +++++++++++++++++++++++-------- 1 file changed, 25 insertions(+), 9 deletions(-) diff --git a/arch/powerpc/platforms/powernv/eeh-ioda.c b/arch/powerpc/platforms/powernv/eeh-ioda.c index 78d94df..cf38781 100644 --- a/arch/powerpc/platforms/powernv/eeh-ioda.c +++ b/arch/powerpc/platforms/powernv/eeh-ioda.c @@ -636,18 +636,34 @@ static int ioda_eeh_bridge_reset(struct pci_dev *dev, int option) return (rc == OPAL_SUCCESS) ? 0 : -EIO; } -void pnv_pci_reset_secondary_bus(struct pci_dev *dev) +static int pnv_pci_dev_reset_type(struct pci_dev *pdev, void *data) { - struct pci_controller *hose; + int *freset = data; - if (pci_is_root_bus(dev->bus)) { - hose = pci_bus_to_host(dev->bus); - ioda_eeh_phb_reset(hose, EEH_RESET_HOT); - ioda_eeh_phb_reset(hose, EEH_RESET_DEACTIVATE); - } else { - ioda_eeh_bridge_reset(dev, EEH_RESET_HOT); - ioda_eeh_bridge_reset(dev, EEH_RESET_DEACTIVATE); + /* + * Stop the iteration immediately if any one PCI + * device requires fundamental reset + */ + *freset |= pdev->needs_freset; + return *freset; +} + +void pnv_pci_reset_secondary_bus(struct pci_dev *pdev) +{ + int option = EEH_RESET_HOT; + int freset = 0; + + /* Check if we need issue fundamental reset */ + if (pdev->subordinate) { + pci_walk_bus(pdev->subordinate, + pnv_pci_dev_reset_type, &freset); + if (freset) + option = EEH_RESET_FUNDAMENTAL; } + + /* Issue required reset type */ + ioda_eeh_bridge_reset(pdev, option); + ioda_eeh_bridge_reset(pdev, EEH_RESET_DEACTIVATE); } /** -- 1.8.3.2