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From: Ian Munsie <imunsie@au1.ibm.com>
To: Ryan Grimm <grimm@linux.vnet.ibm.com>
Subject: Re: [PATCH 1/4] CXL: Use image state defaults for reloading FPGA
In-reply-to: <1421437687-12835-1-git-send-email-grimm@linux.vnet.ibm.com>
References: <1421437687-12835-1-git-send-email-grimm@linux.vnet.ibm.com>
Date: Mon, 19 Jan 2015 16:03:56 +1100
Message-Id: <1421643145-sup-9090@delenn.ozlabs.ibm.com>
Cc: mikey <mikey@neuling.org>, linuxppc-dev <linuxppc-dev@lists.ozlabs.org>,
 Michael Ellerman <michaele@au1.ibm.com>
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Acked-by: Ian Munsie <imunsie@au1.ibm.com>

Looks like you forgot your Signed-off-by line - mpe, do you want Ryan to
resend the whole patch (maybe with the below explanation included), or
just reply with a Signed-off-by?

This would also be good to CC: Stable, as these new defaults mean that
the card will be fully reset when sapphire PERSTs them on reboot,
whereas before it was left up to the default value of this register in
each card, and could lead to a card getting into a bad state requiring a
full power cycle to recover. The symptoms we saw was the tlbia / slbia
we do on boot timing out and the driver init aborting.

Cheers,
-Ian