* [PATCH] powerpc/dts: Update platform PLL node @ 2015-01-12 6:00 Igal.Liberman 2015-01-20 7:43 ` Scott Wood 0 siblings, 1 reply; 5+ messages in thread From: Igal.Liberman @ 2015-01-12 6:00 UTC (permalink / raw) To: linuxppc-dev; +Cc: scottwood, Igal Liberman, Emilian.Medve From: Igal Liberman <Igal.Liberman@freescale.com> Signed-off-by: Igal Liberman <Igal.Liberman@freescale.com> Change-Id: I92d020651237041d3767aa35e9345439714f9831 --- arch/powerpc/boot/dts/fsl/qoriq-clockgen2.dtsi | 6 ++++-- 1 file changed, 4 insertions(+), 2 deletions(-) diff --git a/arch/powerpc/boot/dts/fsl/qoriq-clockgen2.dtsi b/arch/powerpc/boot/dts/fsl/qoriq-clockgen2.dtsi index 48e0b6e..7e1f074 100644 --- a/arch/powerpc/boot/dts/fsl/qoriq-clockgen2.dtsi +++ b/arch/powerpc/boot/dts/fsl/qoriq-clockgen2.dtsi @@ -49,14 +49,16 @@ global-utilities@e1000 { reg = <0x800 0x4>; compatible = "fsl,qoriq-core-pll-2.0"; clocks = <&sysclk>; - clock-output-names = "pll0", "pll0-div2", "pll0-div4"; + clock-output-names = "pll0", "pll0-div2", "pll0-div3", + "pll0-div4"; }; pll1: pll1@820 { #clock-cells = <1>; reg = <0x820 0x4>; compatible = "fsl,qoriq-core-pll-2.0"; clocks = <&sysclk>; - clock-output-names = "pll1", "pll1-div2", "pll1-div4"; + clock-output-names = "pll1", "pll1-div2", "pll1-div3", + "pll1-div4"; }; platform_pll: platform-pll@c00 { #clock-cells = <1>; -- 1.7.9.5 ^ permalink raw reply related [flat|nested] 5+ messages in thread
* Re: [PATCH] powerpc/dts: Update platform PLL node 2015-01-12 6:00 [PATCH] powerpc/dts: Update platform PLL node Igal.Liberman @ 2015-01-20 7:43 ` Scott Wood 2015-01-20 8:51 ` Igal.Liberman 0 siblings, 1 reply; 5+ messages in thread From: Scott Wood @ 2015-01-20 7:43 UTC (permalink / raw) To: Igal.Liberman; +Cc: linuxppc-dev, Emilian.Medve On Mon, 2015-01-12 at 08:00 +0200, Igal.Liberman wrote: > From: Igal Liberman <Igal.Liberman@freescale.com> > > Signed-off-by: Igal Liberman <Igal.Liberman@freescale.com> > Change-Id: I92d020651237041d3767aa35e9345439714f9831 > --- > arch/powerpc/boot/dts/fsl/qoriq-clockgen2.dtsi | 6 ++++-- > 1 file changed, 4 insertions(+), 2 deletions(-) Please explain this more. Was it just wrong before? Is this for a new chip? If the latter, what effect does this have on existing chips? > diff --git a/arch/powerpc/boot/dts/fsl/qoriq-clockgen2.dtsi b/arch/powerpc/boot/dts/fsl/qoriq-clockgen2.dtsi > index 48e0b6e..7e1f074 100644 > --- a/arch/powerpc/boot/dts/fsl/qoriq-clockgen2.dtsi > +++ b/arch/powerpc/boot/dts/fsl/qoriq-clockgen2.dtsi > @@ -49,14 +49,16 @@ global-utilities@e1000 { > reg = <0x800 0x4>; > compatible = "fsl,qoriq-core-pll-2.0"; > clocks = <&sysclk>; > - clock-output-names = "pll0", "pll0-div2", "pll0-div4"; > + clock-output-names = "pll0", "pll0-div2", "pll0-div3", > + "pll0-div4"; You're changing the meaning of existing clock index 2. -Scott ^ permalink raw reply [flat|nested] 5+ messages in thread
* RE: [PATCH] powerpc/dts: Update platform PLL node 2015-01-20 7:43 ` Scott Wood @ 2015-01-20 8:51 ` Igal.Liberman 2015-01-30 4:12 ` Scott Wood 0 siblings, 1 reply; 5+ messages in thread From: Igal.Liberman @ 2015-01-20 8:51 UTC (permalink / raw) To: Scott Wood; +Cc: linuxppc-dev@lists.ozlabs.org, Emilian Medve DQoNClJlZ2FlZHMsDQpJZ2FsIExpYmVybWFuLg0KDQo+IC0tLS0tT3JpZ2luYWwgTWVzc2FnZS0t LS0tDQo+IEZyb206IFdvb2QgU2NvdHQtQjA3NDIxDQo+IFNlbnQ6IFR1ZXNkYXksIEphbnVhcnkg MjAsIDIwMTUgOTo0NCBBTQ0KPiBUbzogTGliZXJtYW4gSWdhbC1CMzE5NTANCj4gQ2M6IGxpbnV4 cHBjLWRldkBsaXN0cy5vemxhYnMub3JnOyBNZWR2ZSBFbWlsaWFuLUVNTUVEVkUxDQo+IFN1Ympl Y3Q6IFJlOiBbUEFUQ0hdIHBvd2VycGMvZHRzOiBVcGRhdGUgcGxhdGZvcm0gUExMIG5vZGUNCj4g DQo+IE9uIE1vbiwgMjAxNS0wMS0xMiBhdCAwODowMCArMDIwMCwgSWdhbC5MaWJlcm1hbiB3cm90 ZToNCj4gPiBGcm9tOiBJZ2FsIExpYmVybWFuIDxJZ2FsLkxpYmVybWFuQGZyZWVzY2FsZS5jb20+ DQo+ID4NCj4gPiBTaWduZWQtb2ZmLWJ5OiBJZ2FsIExpYmVybWFuIDxJZ2FsLkxpYmVybWFuQGZy ZWVzY2FsZS5jb20+DQo+ID4gQ2hhbmdlLUlkOiBJOTJkMDIwNjUxMjM3MDQxZDM3NjdhYTM1ZTkz NDU0Mzk3MTRmOTgzMQ0KPiA+IC0tLQ0KPiA+ICBhcmNoL3Bvd2VycGMvYm9vdC9kdHMvZnNsL3Fv cmlxLWNsb2NrZ2VuMi5kdHNpIHwgICAgNiArKysrLS0NCj4gPiAgMSBmaWxlIGNoYW5nZWQsIDQg aW5zZXJ0aW9ucygrKSwgMiBkZWxldGlvbnMoLSkNCj4gDQo+IFBsZWFzZSBleHBsYWluIHRoaXMg bW9yZS4gIFdhcyBpdCBqdXN0IHdyb25nIGJlZm9yZT8gIElzIHRoaXMgZm9yIGEgbmV3IGNoaXA/ ICBJZg0KPiB0aGUgbGF0dGVyLCB3aGF0IGVmZmVjdCBkb2VzIHRoaXMgaGF2ZSBvbiBleGlzdGlu ZyBjaGlwcz8NCj4gDQoNCkl0IHdhc24ndCB3cm9uZywgaG93ZXZlciBpdCB3YXMgbWlzc2luZyBz b21lIGNsb2NraW5nIG9wdGlvbnMgd2hpY2ggbWlnaHQgYmUgdXNlZCBieSBzb21lIGhhcmR3YXJl IGFjY2VsZXJhdG9ycyBhdmFpbGFibGUgaW4gVC9CIGRldmljZXMuDQpJIG5lZWQgdGhpcyBvcHRp b25zIGZvciBGTWFuLCBob3dldmVyIGl0IG1pZ2h0IGJlIHVzZWQgZm9yIG90aGVyIGFjY2VsZXJh dG9ycyB0b28uDQoNCj4gPiBkaWZmIC0tZ2l0IGEvYXJjaC9wb3dlcnBjL2Jvb3QvZHRzL2ZzbC9x b3JpcS1jbG9ja2dlbjIuZHRzaQ0KPiA+IGIvYXJjaC9wb3dlcnBjL2Jvb3QvZHRzL2ZzbC9xb3Jp cS1jbG9ja2dlbjIuZHRzaQ0KPiA+IGluZGV4IDQ4ZTBiNmUuLjdlMWYwNzQgMTAwNjQ0DQo+ID4g LS0tIGEvYXJjaC9wb3dlcnBjL2Jvb3QvZHRzL2ZzbC9xb3JpcS1jbG9ja2dlbjIuZHRzaQ0KPiA+ ICsrKyBiL2FyY2gvcG93ZXJwYy9ib290L2R0cy9mc2wvcW9yaXEtY2xvY2tnZW4yLmR0c2kNCj4g PiBAQCAtNDksMTQgKzQ5LDE2IEBAIGdsb2JhbC11dGlsaXRpZXNAZTEwMDAgew0KPiA+ICAJCXJl ZyA9IDwweDgwMCAweDQ+Ow0KPiA+ICAJCWNvbXBhdGlibGUgPSAiZnNsLHFvcmlxLWNvcmUtcGxs LTIuMCI7DQo+ID4gIAkJY2xvY2tzID0gPCZzeXNjbGs+Ow0KPiA+IC0JCWNsb2NrLW91dHB1dC1u YW1lcyA9ICJwbGwwIiwgInBsbDAtZGl2MiIsICJwbGwwLWRpdjQiOw0KPiA+ICsJCWNsb2NrLW91 dHB1dC1uYW1lcyA9ICJwbGwwIiwgInBsbDAtZGl2MiIsICJwbGwwLWRpdjMiLA0KPiA+ICsJCQkJ ICAgICAgInBsbDAtZGl2NCI7DQo+IA0KPiBZb3UncmUgY2hhbmdpbmcgdGhlIG1lYW5pbmcgb2Yg ZXhpc3RpbmcgY2xvY2sgaW5kZXggMi4NCj4gDQoNClllcywgaG93ZXZlciB0aGlzIHBsYXRmb3Jt IFBMTCBpcyBhIG5ldyB3b3JrIHdoaWNoIGlzIG5vdCB5ZXQgdXNlZCwgc28gd2UgYXJlbid0IGJy ZWFraW5nIGFueSAgZnVuY3Rpb25hbGl0eS4NCg0KPiAtU2NvdHQNCj4gDQoNCg== ^ permalink raw reply [flat|nested] 5+ messages in thread
* Re: [PATCH] powerpc/dts: Update platform PLL node 2015-01-20 8:51 ` Igal.Liberman @ 2015-01-30 4:12 ` Scott Wood 2015-02-08 13:27 ` Emil Medve 0 siblings, 1 reply; 5+ messages in thread From: Scott Wood @ 2015-01-30 4:12 UTC (permalink / raw) To: Liberman Igal-B31950 Cc: linuxppc-dev@lists.ozlabs.org, Medve Emilian-EMMEDVE1 On Tue, 2015-01-20 at 02:51 -0600, Liberman Igal-B31950 wrote: > > > Regaeds, > Igal Liberman. > > > -----Original Message----- > > From: Wood Scott-B07421 > > Sent: Tuesday, January 20, 2015 9:44 AM > > To: Liberman Igal-B31950 > > Cc: linuxppc-dev@lists.ozlabs.org; Medve Emilian-EMMEDVE1 > > Subject: Re: [PATCH] powerpc/dts: Update platform PLL node > > > > On Mon, 2015-01-12 at 08:00 +0200, Igal.Liberman wrote: > > > From: Igal Liberman <Igal.Liberman@freescale.com> > > > > > > Signed-off-by: Igal Liberman <Igal.Liberman@freescale.com> > > > Change-Id: I92d020651237041d3767aa35e9345439714f9831 > > > --- > > > arch/powerpc/boot/dts/fsl/qoriq-clockgen2.dtsi | 6 ++++-- > > > 1 file changed, 4 insertions(+), 2 deletions(-) > > > > Please explain this more. Was it just wrong before? Is this for a new chip? If > > the latter, what effect does this have on existing chips? > > > > It wasn't wrong, however it was missing some clocking options which > might be used by some hardware accelerators available in T/B devices. > I need this options for FMan, however it might be used for other > accelerators too. If the PLL had a div3 option and it wasn't described by the PLL node, the node was wrong. Do all chips that use this file have a div3? > > > diff --git a/arch/powerpc/boot/dts/fsl/qoriq-clockgen2.dtsi > > > b/arch/powerpc/boot/dts/fsl/qoriq-clockgen2.dtsi > > > index 48e0b6e..7e1f074 100644 > > > --- a/arch/powerpc/boot/dts/fsl/qoriq-clockgen2.dtsi > > > +++ b/arch/powerpc/boot/dts/fsl/qoriq-clockgen2.dtsi > > > @@ -49,14 +49,16 @@ global-utilities@e1000 { > > > reg = <0x800 0x4>; > > > compatible = "fsl,qoriq-core-pll-2.0"; > > > clocks = <&sysclk>; > > > - clock-output-names = "pll0", "pll0-div2", "pll0-div4"; > > > + clock-output-names = "pll0", "pll0-div2", "pll0-div3", > > > + "pll0-div4"; > > > > You're changing the meaning of existing clock index 2. > > > > Yes, however this platform PLL is a new work which is not yet used, so we aren't breaking any functionality. No, it's the core PLL node which is already in use. However, it looks like the driver already interprets clock index 2 differently based on whether clock index 3 exists. None of this is mentioned in the binding document... -Scott ^ permalink raw reply [flat|nested] 5+ messages in thread
* Re: [PATCH] powerpc/dts: Update platform PLL node 2015-01-30 4:12 ` Scott Wood @ 2015-02-08 13:27 ` Emil Medve 0 siblings, 0 replies; 5+ messages in thread From: Emil Medve @ 2015-02-08 13:27 UTC (permalink / raw) To: Scott Wood, Liberman Igal-B31950; +Cc: linuxppc-dev@lists.ozlabs.org Hello Scott, On 01/29/2015 10:12 PM, Scott Wood wrote: >>>> From: Igal Liberman <Igal.Liberman@freescale.com> >>>> >>>> Signed-off-by: Igal Liberman <Igal.Liberman@freescale.com> >>>> Change-Id: I92d020651237041d3767aa35e9345439714f9831 >>>> --- >>>> arch/powerpc/boot/dts/fsl/qoriq-clockgen2.dtsi | 6 ++++-- >>>> 1 file changed, 4 insertions(+), 2 deletions(-) >>> >>> Please explain this more. Was it just wrong before? Is this for a new chip? If >>> the latter, what effect does this have on existing chips? >> >> It wasn't wrong, however it was missing some clocking options which >> might be used by some hardware accelerators available in T/B devices. >> I need this options for FMan, however it might be used for other >> accelerators too. > > If the PLL had a div3 option and it wasn't described by the PLL node, > the node was wrong. Somewhere between early versions of the RM and the cores not using this PLL output, yes the node is incomplete/wrong > Do all chips that use this file have a div3? Yup. T1/2/4, B4, etc. It's used as an input clock to the various IP blocks on said SoC(es), FMan, eSDHC, PME, etc. >>>> diff --git a/arch/powerpc/boot/dts/fsl/qoriq-clockgen2.dtsi >>>> b/arch/powerpc/boot/dts/fsl/qoriq-clockgen2.dtsi >>>> index 48e0b6e..7e1f074 100644 >>>> --- a/arch/powerpc/boot/dts/fsl/qoriq-clockgen2.dtsi >>>> +++ b/arch/powerpc/boot/dts/fsl/qoriq-clockgen2.dtsi >>>> @@ -49,14 +49,16 @@ global-utilities@e1000 { >>>> reg = <0x800 0x4>; >>>> compatible = "fsl,qoriq-core-pll-2.0"; >>>> clocks = <&sysclk>; >>>> - clock-output-names = "pll0", "pll0-div2", "pll0-div4"; >>>> + clock-output-names = "pll0", "pll0-div2", "pll0-div3", >>>> + "pll0-div4"; >>> >>> You're changing the meaning of existing clock index 2. >> >> Yes, however this platform PLL is a new work which is not yet >> used, so we aren't breaking any functionality. > > No, it's the core PLL node which is already in use. However, it looks > like the driver already interprets clock index 2 differently based on > whether clock index 3 exists. None of this is mentioned in the binding > document... Yes, it's a bit fishy and that clock registration (code) ends up working. However, I think we ought to key that code on the chassis version and not on the number of clock outputs in some (in/complete) node instance That being said, there are two outstanding issues: 1. The core mux nodes need to be updated to get pllX-div4 from index 3 not 2. Currently things work because our RCW(s) don't use pllX-div4 so the inconsistency goes unnoticed 2. Chassis v2 supports frequency scaling for the HW accelerators (FMan in this particular case) much like it's supported for the cores (both chassis v1/2). This patch doesn't cover that Cheers, ^ permalink raw reply [flat|nested] 5+ messages in thread
end of thread, other threads:[~2015-02-08 13:28 UTC | newest] Thread overview: 5+ messages (download: mbox.gz follow: Atom feed -- links below jump to the message on this page -- 2015-01-12 6:00 [PATCH] powerpc/dts: Update platform PLL node Igal.Liberman 2015-01-20 7:43 ` Scott Wood 2015-01-20 8:51 ` Igal.Liberman 2015-01-30 4:12 ` Scott Wood 2015-02-08 13:27 ` Emil Medve
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