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Tue, 26 May 2020 07:29:28 +0000 (GMT) Received: from b06wcsmtp001.portsmouth.uk.ibm.com (unknown [127.0.0.1]) by IMSVA (Postfix) with ESMTP id 98F99A405B; Tue, 26 May 2020 07:29:26 +0000 (GMT) Received: from localhost.localdomain (unknown [9.199.55.182]) by b06wcsmtp001.portsmouth.uk.ibm.com (Postfix) with ESMTP; Tue, 26 May 2020 07:29:26 +0000 (GMT) Subject: Re: [PATCH V3 2/2] tools/perf: Add perf tools support for extended register capability in powerpc To: Athira Rajeev , linuxppc-dev@lists.ozlabs.org References: <1589967933-1503-1-git-send-email-atrajeev@linux.vnet.ibm.com> <1589967933-1503-3-git-send-email-atrajeev@linux.vnet.ibm.com> From: Madhavan Srinivasan Message-ID: <142c15f3-d70a-32f9-49a0-2f250fbf0e7d@linux.ibm.com> Date: Tue, 26 May 2020 12:59:25 +0530 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:68.0) Gecko/20100101 Thunderbird/68.8.0 MIME-Version: 1.0 In-Reply-To: <1589967933-1503-3-git-send-email-atrajeev@linux.vnet.ibm.com> Content-Type: text/plain; charset=utf-8; format=flowed Content-Transfer-Encoding: 7bit Content-Language: en-US X-TM-AS-GCONF: 00 X-Proofpoint-Virus-Version: vendor=fsecure engine=2.50.10434:6.0.216, 18.0.687 definitions=2020-05-25_12:2020-05-25, 2020-05-25 signatures=0 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 impostorscore=0 malwarescore=0 suspectscore=0 clxscore=1015 priorityscore=1501 bulkscore=0 lowpriorityscore=0 mlxlogscore=999 phishscore=0 adultscore=0 mlxscore=0 spamscore=0 cotscore=-2147483648 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.12.0-2004280000 definitions=main-2005260049 X-BeenThere: linuxppc-dev@lists.ozlabs.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Linux on PowerPC Developers Mail List List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: ravi.bangoria@linux.ibm.com, maddy@linux.vnet.ibm.com, linux-kernel@vger.kernel.org, acme@kernel.org, anju@linux.vnet.ibm.com, jolsa@kernel.org Errors-To: linuxppc-dev-bounces+linuxppc-dev=archiver.kernel.org@lists.ozlabs.org Sender: "Linuxppc-dev" On 5/20/20 3:15 PM, Athira Rajeev wrote: > From: Anju T Sudhakar > > Add extended regs to sample_reg_mask in the tool side to use > with `-I?` option. Perf tools side uses extended mask to display > the platform supported register names (with -I? option) to the user > and also send this mask to the kernel to capture the extended registers > in each sample. Hence decide the mask value based on the processor > version. > > Signed-off-by: Anju T Sudhakar > [Decide extended mask at run time based on platform] > Signed-off-by: Athira Rajeev Reviewed-by: Madhavan Srinivasan > --- > tools/arch/powerpc/include/uapi/asm/perf_regs.h | 14 ++++++- > tools/perf/arch/powerpc/include/perf_regs.h | 5 ++- > tools/perf/arch/powerpc/util/perf_regs.c | 55 +++++++++++++++++++++++++ > 3 files changed, 72 insertions(+), 2 deletions(-) > > diff --git a/tools/arch/powerpc/include/uapi/asm/perf_regs.h b/tools/arch/powerpc/include/uapi/asm/perf_regs.h > index f599064..485b1d5 100644 > --- a/tools/arch/powerpc/include/uapi/asm/perf_regs.h > +++ b/tools/arch/powerpc/include/uapi/asm/perf_regs.h > @@ -48,6 +48,18 @@ enum perf_event_powerpc_regs { > PERF_REG_POWERPC_DSISR, > PERF_REG_POWERPC_SIER, > PERF_REG_POWERPC_MMCRA, > - PERF_REG_POWERPC_MAX, > + /* Extended registers */ > + PERF_REG_POWERPC_MMCR0, > + PERF_REG_POWERPC_MMCR1, > + PERF_REG_POWERPC_MMCR2, > + /* Max regs without the extended regs */ > + PERF_REG_POWERPC_MAX = PERF_REG_POWERPC_MMCRA + 1, > }; > + > +#define PERF_REG_PMU_MASK ((1ULL << PERF_REG_POWERPC_MAX) - 1) > + > +/* PERF_REG_EXTENDED_MASK value for CPU_FTR_ARCH_300 */ > +#define PERF_REG_PMU_MASK_300 (((1ULL << (PERF_REG_POWERPC_MMCR2 + 1)) - 1) \ > + - PERF_REG_PMU_MASK) > + > #endif /* _UAPI_ASM_POWERPC_PERF_REGS_H */ > diff --git a/tools/perf/arch/powerpc/include/perf_regs.h b/tools/perf/arch/powerpc/include/perf_regs.h > index e18a355..46ed00d 100644 > --- a/tools/perf/arch/powerpc/include/perf_regs.h > +++ b/tools/perf/arch/powerpc/include/perf_regs.h > @@ -64,7 +64,10 @@ > [PERF_REG_POWERPC_DAR] = "dar", > [PERF_REG_POWERPC_DSISR] = "dsisr", > [PERF_REG_POWERPC_SIER] = "sier", > - [PERF_REG_POWERPC_MMCRA] = "mmcra" > + [PERF_REG_POWERPC_MMCRA] = "mmcra", > + [PERF_REG_POWERPC_MMCR0] = "mmcr0", > + [PERF_REG_POWERPC_MMCR1] = "mmcr1", > + [PERF_REG_POWERPC_MMCR2] = "mmcr2", > }; > > static inline const char *perf_reg_name(int id) > diff --git a/tools/perf/arch/powerpc/util/perf_regs.c b/tools/perf/arch/powerpc/util/perf_regs.c > index 0a52429..9179230 100644 > --- a/tools/perf/arch/powerpc/util/perf_regs.c > +++ b/tools/perf/arch/powerpc/util/perf_regs.c > @@ -6,9 +6,14 @@ > > #include "../../../util/perf_regs.h" > #include "../../../util/debug.h" > +#include "../../../util/event.h" > +#include "../../../util/header.h" > +#include "../../../perf-sys.h" > > #include > > +#define PVR_POWER9 0x004E > + > const struct sample_reg sample_reg_masks[] = { > SMPL_REG(r0, PERF_REG_POWERPC_R0), > SMPL_REG(r1, PERF_REG_POWERPC_R1), > @@ -55,6 +60,9 @@ > SMPL_REG(dsisr, PERF_REG_POWERPC_DSISR), > SMPL_REG(sier, PERF_REG_POWERPC_SIER), > SMPL_REG(mmcra, PERF_REG_POWERPC_MMCRA), > + SMPL_REG(mmcr0, PERF_REG_POWERPC_MMCR0), > + SMPL_REG(mmcr1, PERF_REG_POWERPC_MMCR1), > + SMPL_REG(mmcr2, PERF_REG_POWERPC_MMCR2), > SMPL_REG_END > }; > > @@ -163,3 +171,50 @@ int arch_sdt_arg_parse_op(char *old_op, char **new_op) > > return SDT_ARG_VALID; > } > + > +uint64_t arch__intr_reg_mask(void) > +{ > + struct perf_event_attr attr = { > + .type = PERF_TYPE_HARDWARE, > + .config = PERF_COUNT_HW_CPU_CYCLES, > + .sample_type = PERF_SAMPLE_REGS_INTR, > + .precise_ip = 1, > + .disabled = 1, > + .exclude_kernel = 1, > + }; > + int fd, ret; > + char buffer[64]; > + u32 version; > + u64 extended_mask = 0; > + > + /* Get the PVR value to set the extended > + * mask specific to platform > + */ > + get_cpuid(buffer, sizeof(buffer)); > + ret = sscanf(buffer, "%u,", &version); > + > + if (ret != 1) { > + pr_debug("Failed to get the processor version, unable to output extended registers\n"); > + return PERF_REGS_MASK; > + } > + > + if (version == PVR_POWER9) > + extended_mask = PERF_REG_PMU_MASK_300; > + else > + return PERF_REGS_MASK; > + > + attr.sample_regs_intr = extended_mask; > + attr.sample_period = 1; > + event_attr_init(&attr); > + > + /* > + * check if the pmu supports perf extended regs, before > + * returning the register mask to sample. > + */ > + fd = sys_perf_event_open(&attr, 0, -1, -1, 0); > + if (fd != -1) { > + close(fd); > + return (extended_mask | PERF_REGS_MASK); > + } > + return PERF_REGS_MASK; > +}